Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

An apparatus for monitoring radio frequency (RF) signals is disclosed. The apparatus includes an RF splitter, a set of track-and-hold circuits, a set of analog-to-digital circuits (ADC) and a frequency tracking module. The RF splitter splits a set of incoming RF signals into multiple RF signal paths. Each of the track-and-hold circuits, which is clocked at a different frequency than others, samples the incoming RF signals from a respective one of the RF signal paths. Each of the ADCs receives the sampled data from a respective one of the track-and-hold circuits. Each of the ADCs is also clocked at same frequency as a corresponding one of the track-and-hold circuits. The frequency tracking module determines a frequency of the incoming RF signals.

Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.

A receiver receives a load modulated analog input signal and outputs digital data detected in the input signal. An in-phase correlator and a quadrature-phase correlator for each of an in-phase component and an quadrature-phase component correlate the in-phase component and the quadrature-component with an in-phase component and a quadrature-phase component of a subcarrier or code clock frequency of the input signal. A combiner combines four output signals of the two in-phase correlators and the two quadrature-phase correlators. A slicer samples an output signal of the combiner at maximum energy levels to output the digital data detected in the input signal.

A frequency-to-voltage (F2V) conversion module includes a pulse shaping module that generates a square wave signal based on an oscillator signal, an edge to pulse conversion module that generates a pulse train based on corresponding rising and falling edges of the square wave signal, and an integrator module that generates an output voltage based on the pulse train. The output voltage is based on a frequency of the oscillator signal.

A frequency-to-voltage (F2V) conversion module includes a pulse shaping module that generates a square wave signal based on an oscillator signal, an edge to pulse conversion module that generates a pulse train based on corresponding rising and falling edges of the square wave signal, and an integrator module that generates an output voltage based on the pulse train. The output voltage is based on a frequency of the oscillator signal.

A frequency-to-voltage (F2V) conversion module includes a pulse shaping module that generates a square wave signal based on an oscillator signal, an edge to pulse conversion module that generates a pulse train based on corresponding rising and falling edges of the square wave signal, and an integrator module that generates an output voltage based on the pulse train. The output voltage is based on a frequency of the oscillator signal.

A frequency-to-voltage (F2V) conversion module includes a pulse shaping module that generates a square wave signal based on an oscillator signal, an edge to pulse conversion module that generates a pulse train based on corresponding rising and falling edges of the square wave signal, and an integrator module that generates an output voltage based on the pulse train. The output voltage is based on a frequency of the oscillator signal.

A communications adaptor comprises a receiver circuit, which can comprise a signal input configured to receive a frequency shift keyed (FSK) signal; a delay circuit in communication with the signal input and including a delayed signal output; a multiplier circuit in communication with the signal input and the delayed signal output, and the multiplier circuit can be configured to produce a serial bit steam from at least the signal input and the delayed signal output, the serial bit stream corresponds to one or more bits encoded with frequency shift keying in the FSK signal; and a signal output configured to output the serial bit stream. The communications adaptor also can comprise a transmitter circuit and a processor in communication with the receiver circuit and the transmitter circuit.