Systems and methods for digital signal processing are provided. A method includes mapping a symbol in a pulse sequence by using a pulse width and a pulse start in the symbol, reading a message using a symbol value for each symbol in a string of symbols, and modifying a drilling configuration according to the message. A device configured to perform the above method is also provided.

Systems and methods for digital signal processing are provided. A method includes mapping a symbol in a pulse sequence by using a pulse width and a pulse start in the symbol, reading a message using a symbol value for each symbol in a string of symbols, and modifying a drilling configuration according to the message. A device configured to perform the above method is also provided.

The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage V.sub.C, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage V.sub.C. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.

The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage V.sub.C, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage V.sub.C. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.

A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.

A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.

An image processing apparatus includes (A) a dither processing unit to perform dither processing on first image data to generate second image data, the second image data including a target pixel and an adjacent pixel, each of the pixels having a density value, the density value of the target pixel being greater than that of the adjacent pixel, and the density value of the adjacent pixel being not greater than a predetermined density, (B) a diffusing unit (a) to determine an error value resulting at the target pixel, (b) to diffuse the error value to pixels subsequent to the target pixel, and not to diffuse an error value resulting at the adjacent pixel to pixels subsequent to the adjacent pixel.

An image processing apparatus includes (A) a dither processing unit to perform dither processing on first image data to generate second image data, the second image data including a target pixel and an adjacent pixel, each of the pixels having a density value, the density value of the target pixel being greater than that of the adjacent pixel, and the density value of the adjacent pixel being not greater than a predetermined density, (B) a diffusing unit (a) to determine an error value resulting at the target pixel, (b) to diffuse the error value to pixels subsequent to the target pixel, and not to diffuse an error value resulting at the adjacent pixel to pixels subsequent to the adjacent pixel.

The present invention relates to a system and a method for pulse width modulation and demodulation of a continuous input signal, which system is configured to receive a continuous input to an analog modulator, which system comprises a demodulator generating a continuous output signal. It is the object of the pending patent application to use an analog modulator for transmitting the signal from the input stage over to an output stage. A further object of the pending patent application is to preserve the signal integrity in regard to precision and to minimize both non-linearities and distortion side effects. The object can be fulfilled by the analog modulator being formed as a composite phase modulator which composite phase modulator comprises at least one feedback loop which feedback loop determines the width of a low-level discrete signal, which composite phase modulator comprises at least one feed-forward loop, which feed-forward loop determines the width of a high-level discrete signal as a function of the continuous input. Hereby it can be achieved that timing between discrete low-level and high-level forms a discontinuous output signal representing the continuous input.

The present invention relates to a system and a method for pulse width modulation and demodulation of a continuous input signal, which system is configured to receive a continuous input to an analog modulator, which system comprises a demodulator generating a continuous output signal. It is the object of the pending patent application to use an analog modulator for transmitting the signal from the input stage over to an output stage. A further object of the pending patent application is to preserve the signal integrity in regard to precision and to minimize both non-linearities and distortion side effects. The object can be fulfilled by the analog modulator being formed as a composite phase modulator which composite phase modulator comprises at least one feedback loop which feedback loop determines the width of a low-level discrete signal, which composite phase modulator comprises at least one feed-forward loop, which feed-forward loop determines the width of a high-level discrete signal as a function of the continuous input. Hereby it can be achieved that timing between discrete low-level and high-level forms a discontinuous output signal representing the continuous input.