A signal detection circuit includes: a voltage dividing circuit having at least a first pair of voltage dividing capacitors connected in series for dividing an input voltage and configured to output a divided voltage, and a detection circuit configured to detect the divided voltage. The first pair of voltage dividing capacitors are included in one semiconductor device. The semiconductor device includes: (i) a semiconductor substrate, (ii) a first conductor layer, (iii) a first dielectric layer, (iv) a second conductor layer, (v) a second dielectric layer, (vi) a third conductor layer, and (vii) a short-circuit portion configured to short-circuit the first conductor layer and the semiconductor substrate.

A control device includes a first series circuit and a second series circuit. In the first series circuit, a first switch and a first resistor are connected in series to each other. In the second series circuit, a second switch and a second resistor are connected in series to each other. A current detection circuit outputs a voltage value that corresponds to a voltage value between two ends of the first resistor. When an instruction to turn on the first switch and the second switch has been given, a control unit senses any occurrence of a failure in at least one of the first switch, the second switch, the first resistor, and the second resistor, based on the voltage value output by the current detection circuit.

A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.

An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

A staged circuit includes a plurality of switching elements in series. Each of the switching elements includes two switches operated in concert. Separate but correlated clock signals drive the switches of each switching element. Switch timing for the switches in each switching element is tuned via certain delays to produce transients with variable characteristics. Furthermore, the number of switching elements may be adjusted to produce transients with variable characteristics. The staged circuit defines a time-varying transmission line and can be used as a driver for a NLTL source.

A multi-channel switch device is provided. The multi-channel switch device includes a first-stage switch circuit, at least one second-stage switch circuit, and multiple third-stage switch circuits. The first-stage switch circuit includes a first common-mode node, a first input/output terminal, and at least one first-stage connection terminal. The second-stage switch circuit includes a second common-mode node, a second-stage transmission terminal, and multiple second-stage connection terminals. Each of the third-stage switch circuits includes a third common-mode node, a third-stage transmission terminal, a reference terminal, and a second input/output terminal. Two of the first input/output terminal and the at least one first-stage connection terminal are connected through the first common-mode node. Two of the second-stage transmission terminal and the second-stage connection terminals are connected through the second common-mode node. Two of the third-stage transmission terminal, the reference terminal, and the second input/output terminal are connected through the third common-mode node.

A circuit architecture and process that provides for a dual-mode methodology for an RF integrated circuit (IC) switch circuit that allows switching between a direct mapping configuration and a fully decoded mapping configuration, and further provides for changing either mapping configuration after fabrication. A control word is selectively compared to a programmed map register value so that, in a first mode, only one bit position of a control word matches a decoded programmed map bit pattern, and in a second mode, all bits of a control word match a corresponding programmed map bit pattern. Because the map registers can be programmed at least once after IC fabrication, the exact mapping required for a particular application can be determined post fabrication. Further, the first mode of operation is often beneficial during testing because multiple RF signal paths can be turned on at the same time and thus tested in parallel.

A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.

A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.

A selection circuit includes at least three control terminals; wherein: a first group of the at least three control terminals is configured to provide a first signal for controlling a first function; and a second group of the at least three control terminals is also configured to provide a second signal for controlling the first function.