In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.

A switch circuit configured to receive power from either a single power source or dual power source. The circuit includes two power input terminals and two power output terminals. For a single power source, the switch circuit may receive the single power source at either of the two power input terminals. The switch circuit provides power to a load without regard to which of the power input terminals the single power source is connected. The switch circuit shorts the power output terminals for a single power input, which provides power at both power output terminals. For a dual power source system, the switch circuit may isolate the two power output terminals so each power output terminal may operate independently without shorting. In some examples, the switch circuit may be part of a thermostat or similar HVAC system controller.

A selection circuit architecture makes it possible to perform upward and/or downward transitions in sets of sequences of slow and fast phases so as at the same time to solve the problems of inductive switching noise and the problems of currents in the supply rails. This solution has multiple advantages linked to the ease of implementation and flexibility of configurations that are possible for adapting to the specific constraints when designing the circuit.

A staged circuit includes a plurality of switching elements in series. Each of the switching elements includes two switches operated in concert. Separate but correlated clock signals drive the switches of each switching element. Switch timing for the switches in each switching element is tuned via certain delays to produce transients with variable characteristics. Furthermore, the number of switching elements may be adjusted to produce transients with variable characteristics. The staged circuit defines a time-varying transmission line and can be used as a driver for a NLTL source.

A control system for independent alternating-input (“IAI”) devices includes multiple IAI devices and an analog switch component. The control system may also include a bus-generating component. The analog switch component includes multiple switches configured to connect of disconnect input connection points of the analog switch component and voltage input points of the IAI devices. The analog switch component opens or closes switches, responsive to a digital control signal, to provide voltage signals to the voltage input points of the IAI devices. In some cases, the IAI devices activate or deactivate based on the provided voltage signals. In some cases, the bus-generating component provides a first voltage signal to a first voltage input point of an IAI device, and the analog switch component controls the switches to provide a second voltage signal to a second voltage input point of the IAI device.

A power storage apparatus includes a power storage unit including a plurality of power storage devices (C1, C2) storing electric power, a series-and-parallel switching unit configured to switch connection of the plurality of power storage devices into a series connection or a parallel connection, and a series-and-parallel switching control unit configured to control the series-and-parallel switching unit, wherein the series-and-parallel switching control unit controls timing of the switching with hysteresis.

An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

An apparatus is provided comprising a first t-switch, which includes an input port arranged to be connected to a first voltage source, a center-tap port, and an output port arranged to be connected to a load. The first t-switch is configured to connect the input port to the output port in an on mode and disconnect the input port from the output port in an off mode. The apparatus further comprises a bias voltage generation circuit configured to generate a bias voltage, the generated bias voltage coupled to the center-tap port of the first t-switch, the bias voltage determined based upon an output port voltage.

A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.

A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.