A gate drive circuit includes a driver for driving a gate of a switching element, a peak voltage detector, and a drive capacity calculator. The peak voltage detector detects a peak voltage at a main terminal of the switching element when the switching element is OFF. The drive capacity calculator calculates a voltage difference value between the detected peak voltage and an allowable voltage value at the main terminal of the switching element, where the allowable voltage is based on the specifications of the switching element. The drive capacity calculator changes a drive capacity of the driver to gradually decrease the difference between the detected peak voltage and the allowable voltage.

A circuit arrangement for a control unit of a vehicle. The circuit arrangement includes at least one ASIC component, which comprises at least one analog input and at least one analog output, and at least one multiplexer which comprises at least one output that is electrically connected to the at least one analog input and at least two inputs and is embodied to electrically connect one of the at least two inputs to the at least one output as a function of at least one control signal. The at least one ASIC component has a multiplexer function which is embodied to generate the at least one control signal and to output the signal via the at least one analog output to at least one control input of the at least one multiplexer. A control unit comprising at least one such circuit arrangement is also described.

A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

A device for hooking up a signal-outputting mechanism with two potential sensors each of which has allocated to it two evaluation terminals, wherein the potentials of the evaluation terminals depend inversely on the resistances between the respective evaluation terminals.

A control device includes a first series circuit and a second series circuit. In the first series circuit, a first switch and a first resistor are connected in series to each other. In the second series circuit, a second switch and a second resistor are connected in series to each other. A current detection circuit outputs a voltage value that corresponds to a voltage value between two ends of the first resistor. When an instruction to turn on the first switch and the second switch has been given, a control unit senses any occurrence of a failure in at least one of the first switch, the second switch, the first resistor, and the second resistor, based on the voltage value output by the current detection circuit.

A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

A multiplexer is provided herein. The multiplexer has a plurality of first driving units and a plurality of second driving units. Each of the first driving units has a first data voltage input terminal, and each of the second driving units has a second data voltage input terminal. The first data voltage input terminal and the second data voltage input terminal are configured to receive pixel voltage signals with different polarities. In the first driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a first reset signal, wherein the transistor of the first driving unit is coupled to the first data voltage input terminal and a first data line. In the second driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a second reset signal, wherein the transistor of the second driving unit is coupled to the second data voltage input terminal and a second data line.

An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.