A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

A drive circuit includes a second drive circuit that drives a semiconductor switching element in a case where a pulse width of a corresponding signal is determined to be larger than a second threshold, and a timing adjustment circuit that adjusts a timing at which the second drive circuit cooperates with a first drive circuit to drive the semiconductor switching element during a turn-off period of the semiconductor switching element due to drive of the first drive circuit.

A drive circuit includes a second drive circuit that drives a semiconductor switching element in a case where a pulse width of a corresponding signal is determined to be larger than a second threshold, and a timing adjustment circuit that adjusts a timing at which the second drive circuit cooperates with a first drive circuit to drive the semiconductor switching element during a turn-off period of the semiconductor switching element due to drive of the first drive circuit.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

A drive circuit includes a second drive circuit that drives a semiconductor switching element in a case where a pulse width of a corresponding signal is determined to be larger than a second threshold, and a timing adjustment circuit that adjusts a timing at which the second drive circuit cooperates with a first drive circuit to drive the semiconductor switching element during a turn-off period of the semiconductor switching element due to drive of the first drive circuit.

A drive circuit includes a second drive circuit that drives a semiconductor switching element in a case where a pulse width of a corresponding signal is determined to be larger than a second threshold, and a timing adjustment circuit that adjusts a timing at which the second drive circuit cooperates with a first drive circuit to drive the semiconductor switching element during a turn-off period of the semiconductor switching element due to drive of the first drive circuit.

Disclosed herein is a hybrid resonant capacitor circuit including a first capacitor configured to discharge resonant current to interrupt a load current to a switch in parallel with the hybrid resonant capacitor circuit, a second capacitor coupled in parallel with the first capacitor, wherein the second capacitor is configured to transfer energy stored in the second capacitor to the first capacitor after discharge of the resonant current from the first capacitor, and a current limiter coupled in series with the second capacitor. A static transfer switch including a thyristor switch and the hybrid resonant capacitor circuit is also disclosed herein, as is a method for facilitating multiple consecutive voltage source transfers between a first voltage source and a second voltage source powering a load, using the hybrid resonant capacitor circuit.

A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.