A semiconductor device of an embodiment includes semiconductor layer including first and second planes, and in order from the first plane's side to the second plane's side, first region of first conductivity type, second region of second conductivity type, third region of second conductivity type having second conductivity type impurity concentration higher than the second region, fourth region of first conductivity type, and fifth region of second conductivity type, and including first and second trench on the first plane's side; first gate electrode in the first trench; first gate insulating film in contact with the fifth semiconductor region; second gate electrode in the second trench; second gate insulating film; a first electrode on the first plane; second electrode on the second plane; first gate electrode pad connected to the first gate electrode; and second gate electrode pad connected to the second gate electrode.

Disclosed herein is a hybrid resonant capacitor circuit including a first capacitor configured to discharge resonant current to interrupt a load current to a switch in parallel with the hybrid resonant capacitor circuit, a second capacitor coupled in parallel with the first capacitor, wherein the second capacitor is configured to transfer energy stored in the second capacitor to the first capacitor after discharge of the resonant current from the first capacitor, and a current limiter coupled in series with the second capacitor. A static transfer switch including a thyristor switch and the hybrid resonant capacitor circuit is also disclosed herein, as is a method for facilitating multiple consecutive voltage source transfers between a first voltage source and a second voltage source powering a load, using the hybrid resonant capacitor circuit.

A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

A bootstrap circuit supporting fast charging and discharging and a chip. A voltage measurement module (12) and a switch module (11) are arranged, and the voltage measurement module (12) controls an operating state of the switch module (11); during charging, under a specific condition, the switch module (11) is enabled to be in an on state so as to achieve fast charging of a voltage output end; and during discharging, the purpose of fast discharging is achieved by means of a second field effect transistor (MP5) arranged in the bootstrap circuit.

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

An information representation method, a multi-value calculation circuit and an electronic system are provided. The information representation method includes: acquiring a switching rate of a signal; and adopting the switching rate of the signal to represent information.

An information representation method, a multi-value calculation circuit and an electronic system are provided. The information representation method includes: acquiring a switching rate of a signal; and adopting the switching rate of the signal to represent information.

A semiconductor device including a first line configured to receive a power supply voltage, a second line configured to be coupled to a load of the semiconductor device, first and second metal-oxide-semiconductor (MOS) transistors coupled in series between the first line and the second line, each of the first and second MOS transistors having a drain electrode and a gate electrode, the drain electrode of the first MOS transistor being coupled to the drain electrode of the second MOS transistor, a third line coupled to the gate electrode of the first MOS transistor, and a fourth line coupled to the gate electrode of the second MOS transistor, the third and fourth lines being electrically separated from each other.