An electronic device includes at least one electronic component, a gradient heat-flux sensor GHFS based on thermoelectric anisotropy and conducting heat generated by the electronic component, and a controller adapted to manage electrical current of the electronic component at least partly on the basis of an electrical control signal generated by the gradient heat-flux sensor and proportional to a heat-flux through the gradient heat-flux sensor. Therefore, the electrical current and thereby also the heat generation of the electronic component are managed directly on the basis of the heat-flux generated by the electronic component. Thus, the electrical current can be managed without a need for voltage and current measurements which may be challenging to be carried out with a sufficient bandwidth especially when the switching frequency of the electronic component is on a range from hundreds of kHz to few MHz.

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

Passive gate bias network topologies are implemented for stacked FET switch structures, which improve the settling time and low cut-off frequency for both DC and non-DC operation. DC capable stacked switch bias structures provide gate and bulk bias voltages, using input DC voltages, which are coupled to the gate terminals and the bulk terminals of the stacked switches. The DC coupling can be achieved using resistors, or a combination of resistors and diodes. An exemplary SPST switch includes a series stacked switch in combination with a shunt stacked switch, which can be controlled between alternating states. For low cut-off frequency improvement structures, an input signal is coupled to the gate terminals and bulk terminals of the switches in the stacked switches, using a DC block capacitor and resistors. The low cut-off of the bulk can be improved by connecting the bulk terminal of one switch to the opposite polarity switch.

The invention relates to a method (10) and to a device (ALE) for operating a switching element (LHS), said method comprising the following steps: a temperature (Tmp) of the switching element (LHS) is determined (22) and said switching element (LHS) is operated (26) in accordance with the determined temperature (TmP).

In general, according to one embodiment, a semiconductor device includes an input terminal, an output terminal, and a plurality of transistors. The transistors are coupled through serial coupling. The transistors include a first transistor and a second transistor. The first transistor has a first end and a second end. The second transistor has a third end, a fourth end, a first gate, and a first body. The third end is coupled to the second end. The semiconductor device further includes a third transistor and a first diode. The third transistor and the first diode are serially coupled between the first body and the first end. The third transistor includes a second gate coupled to the first gate.

A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by V.sub.th, a maximum rated gate voltage of the normally-off transistor is denoted by V.sub.g_max, a voltage of the fourth end portion is denoted by V.sub.g_on, the first capacitance component is denoted by C.sub.a, and the second capacitance component is denoted by C.sub.b, V.sub.th<(C.sub.b/(C.sub.a+C.sub.b))V.sub.g_on<V.sub.g_max.

A switching unit of an embodiment includes a first switching element of normally-on type, a second switching element of normally-off type having a non-reference potential side conductive terminal connected to a reference potential side conductive terminal of the first switching element, a series capacitor connected between a conduction control terminal of the first switching element and a conduction control terminal of the second switching element, and a diode having an anode connected to the conduction control terminal of the first switching element and a cathode connected to a common junction of the first switching element and the second switching element.

An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.