A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

A circuit comprises a first field-effect transistor (FET) having a first gate, a first source, and a first drain, a first resistor, a first voltage generator, a second FET having a second gate, a second source, and a second drain, and coupling circuitry configured to couple the first resistor to the first gate, the first voltage generator to the first resistor and ground, and the second FET in parallel with the first resistor.

In one embodiment, a circuit includes a plurality of elementary transistors connected in parallel between a node of application of a first potential of a power supply voltage and a node for coupling a load. The plurality of transistors includes a first assembly of elementary transistors having their gates coupled to a control node by a first circuit and a second assembly of elementary transistors having their gates coupled to the control node by a second circuit. The second circuit has two states, where the first and second circuits are configured to supply a substantially identical control voltage to the gates of the first and second assemblies of elementary transistors when the second circuit is in one of the two states.

In at least one general aspect, an apparatus can include a first field effect transistor (FET) device and a second FET device. The apparatus can include a characterization circuit coupled to the first FET device and the second FET device where the characterization circuit can be configured to characterize a responsiveness of each of the first FET device and the second FET device. The apparatus can include a balancer configured to produce a modified gate drive signal for the first FET device based on the responsiveness of the first FET device.

A switch circuit electrically connected to a power source and a first control source and including a plurality of switch bridge arms is provided. Each of the plurality of switch bridge arms includes a first switch and a second switch electrically connected in series. A loop formed by the first switch, the second switch and the power source is defined as a power loop. A loop formed by the first control source and the first switch is defined as a first control loop. A first mutual inductance is formed between the power loop and the first control loop. Among all the first switches, the first switch with the longer power loop has the smaller first mutual inductance.

A switching apparatus electrically connects an electrical load to an energy source and contains a main current path which has a switching unit with a circuit breaker, via which the electrical load is connected to the energy source in a supply mode. An auxiliary current path is connected in parallel with the main current path and in which a first switch is arranged. A disconnection mode is performed in which the circuit breaker is open and the electrical load is connected only to the auxiliary current path to reduce electrical energy stored inside the electrical load. A diagnostic mode is also provided, in which the switching unit is open and the electrical load is connected to the energy source only via the auxiliary current path to supply the electrical load. A control unit for activating the diagnostic mode is also provided.

A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.

An electronic switching circuit, in particular a solid state relay, provides bidirectional electronic power switching. The circuit can be connected to a load and an electrical voltage source. It includes two field effect transistors and a control circuit. The control circuit is conductively connected to the respective gate terminal of the field effect transistors. The field effect transistors are connected in an anti-serial configuration.

A driver circuit includes two high-side switches and a single low-side switch, output inductor, and output capacitor. By having multiple high-side switches, the driver can regulate power from multiple charging devices. The high-side switches share a channel with an input capacitor for that channel and the channels are connected to the low-side switch at a common node. When the capacitor for one of the channels becomes charged quickly, the capacitor of the other channel will balance itself with the charged capacitor. To avoid damaging the high-side switches, a low-impedance bridge and driver circuit is connected between the channels.

A gate drive circuit includes a signal generation unit configured to generate a first gate drive signal, a signal isolation unit configured to produce, at an output side thereof in response to the first gate drive signal, a second gate drive signal electrically isolated from the signal generation unit, an output stage device configured to receive the second gate drive signal at an input side thereof and to produce a third gate drive signal at an output side thereof in response to the second gate drive signal, a first path connecting the output side of the signal isolation unit and the input side of the output stage device; and a second path connecting the output side of the signal isolation unit and the output side of the output stage device.