Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

A voltage detection circuit including an input voltage stage configured to scale down an input voltage to produce a scaled down voltage, a gain loss stage configured to receive and adjust the scaled down voltage based on a determined gain or loss to be applied to the scaled down voltage, and a comparison circuit configured to determine if the input voltage is over or under a desired voltage value.

A hybrid switch apparatus includes a standard semiconductor switch and a fast semiconductor switch electrically arranged in parallel to form a joint output current path for carrying a load current. The standard switch may be a silicon (Si) MOSFET while the fast switch may be a GaN high electron mobility transistor (HEMT). A means for producing first and second gate drive signals includes a pulse former. The first gate drive signal is applied the standard switch for selectively turning the standard switch on and off. The pulse former outputs the second gate drive signal for driving the fast switch, where the pulse former generates the second gate drive signal as a switch-on pulse starting synchronously with each transition of the first gate drive signal and which generates the second gate drive signal in an OFF state in between pulses to avoid incurring a conduction loss in the fast switch.

A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.

A switched-mode power converter and a method for operation is presented. The switched-mode power converter has a high side switching element, a low side switching element, and an inductor. Both the high side switching element and the low side switching element are coupled to an input terminal of the inductor. A zero cross comparator generates a trigger signal for opening the low side switching element. A sampling unit samples, at a time when the low side switching element is switching, an inductor voltage at the input terminal of the inductor. An integrating unit determines an offset voltage by integrating the sampled inductor voltage. Finally, an input voltage of the zero cross comparator is adjusted by subtracting the determined offset voltage from the inductor voltage. As a result, the switching behavior of the switched-mode power converter is optimized.

A semiconductor device includes IGBT devices; and a freewheeling diode provided for each IGBT device. The IGBT devices are connected in parallel to be driven. Each IGBT device includes: a collector region; a drift region; a body region; a trench gate penetrating the body region; and an emitter region surrounded by the body region and in contact with the trench gate. Each IGBT device further includes an active cell with the emitter region; a dummy cell without the emitter region; and an active dummy cell without the emitter region. The active dummy cell has a float cell where the body region is in electrically-floating condition. A ratio of the number of float cell to the total number of the active cell and the active dummy cell is larger than or equal to 5% and is smaller than or equal to 35%.

A semiconductor device includes a plurality of switching devices and a semiconductor substrate. The switching devices are connected in parallel to be driven. The switching devices are at the semiconductor substrate. Each of the switching devices, in a plan view of the semiconductor substrate, includes: a cell region as an IGBT that is provided with an active trench gate to be applied with a gate voltage; a periphery region as a contour of the switching device; and a non-cell region configured to isolate the cell region from the periphery region and arranged with a pad to provide an electrical connection to the cell region. The non-cell region is also provided with an active trench gate that is at a position without overlapping the pad.

A switch of an inverter of an X-ray tube power supply including: at least four MOSFETs aligned in parallel; a plurality of intermediate radiators positioned between the MOSFETs in order to separate two successive MOSFETs; at least four snubbers positioned in parallel, each being positioned beside a MOSFET; a control unit of said switch positioned so that the succession of MOSFETs is positioned between the alignment of snubbers and the control unit.

A system balances current flowing through a solid-state power controller system including at least two output channels connected in parallel. The system delivers a first current to a load via a first output channel to a load, and delivers a second current to the load via a second output channel connected in parallel with the first output channel. The system further determines a first strength of the first current and a second strength of the second current, and adjusts at least one of a first resistance of the first output channel and a second resistance of the second output channel such that the first current strength is substantially equal to the second current strength.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.