The present disclosure relates to a semiconductor switch leg S for a Power Electronic (PE) converter (1). The switch leg comprises a plurality of parallel connected semiconductor devices Sa-d. Each semiconductor device is connected with a positive conductor a-d+ connecting the semiconductor device to a positive terminal of an energy storing device (2) of the converter, and a negative conductor a-d-connecting the semiconductor device to a negative terminal of the energy storing device (2) of the converter, the semiconductor device together with the positive conductor and the negative conductor forming a current path across the energy storing device. The semiconductor switch leg comprises a plurality of magnetic coupling devices 3a-d, each magnetic coupling device being arranged between the two current paths of respective two neighbouring semiconductor devices of the plurality of semiconductor devices such that the current path of one of the two semiconductor devices and the current path of the other of the two semiconductor devices

The present disclosure relates to a semiconductor switch leg S for a Power Electronic (PE) converter (1). The switch leg comprises a plurality of parallel connected semiconductor devices Sa-d. Each semiconductor device is connected with a positive conductor a-d+ connecting the semiconductor device to a positive terminal of an energy storing device (2) of the converter, and a negative conductor a-d-connecting the semiconductor device to a negative terminal of the energy storing device (2) of the converter, the semiconductor device together with the positive conductor and the negative conductor forming a current path across the energy storing device. The semiconductor switch leg comprises a plurality of magnetic coupling devices 3a-d, each magnetic coupling device being arranged between the two current paths of respective two neighbouring semiconductor devices of the plurality of semiconductor devices such that the current path of one of the two semiconductor devices and the current path of the other of the two semiconductor devices

A power conversion apparatus is provided in which an upper arm semiconductor device, a lower arm semiconductor device and a capacitor. At least either upper arm semiconductor device or lower arm semiconductor device constitutes a parallel-connected body. In an opposite arm against the parallel-connected body, a permissible element is provided. In the switching elements that constitute the parallel-connected body, a last off element and a non-last off circuit are identified. Inductance of a last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor is smaller than inductance of a non-last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor.

A power conversion apparatus is provided in which an upper arm semiconductor device, a lower arm semiconductor device and a capacitor. At least either upper arm semiconductor device or lower arm semiconductor device constitutes a parallel-connected body. In an opposite arm against the parallel-connected body, a permissible element is provided. In the switching elements that constitute the parallel-connected body, a last off element and a non-last off circuit are identified. Inductance of a last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor is smaller than inductance of a non-last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor.

A method and arrangement for controlling semiconductor power switches, e.g. IGBTs, in parallel connected power devices, e.g. in frequency converters, wherein the semiconductor power switches connect either the positive or the negative pole of the intermediate DC-voltage of the power device to an output phase of the power device. In the method the voltages of those output phases which are connected in parallel are measured, the timing differences of the output voltage state changes are calculated on the basis of the output voltage measurement results, and the control signals of the semiconductor power switches are advanced or delayed such that the output voltage state changes in the phases which are connected together via output impedances occur at desired time instants.

A control device for controlling a power semiconductor component which includes at least two voltage-controlled power semiconductor devices which are electrically connected in parallel and which have each a control connection is disclosed. The control device includes a driver element which can be used to set electrical voltages at the control connections of the power semiconductor devices. The control device includes a measuring unit configured to capture electrical currents which flow through the power semiconductor devices. The driver element is configured to set a level and/or a temporal profile of the electrical voltages on the basis of the electrical currents.

A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

The present invention concerns a device for controlling the operation of a power module composed of switches, each switch being composed of a plurality of power dies connected in parallel, characterized in that the device comprises, for each power die of the power module: a temperature sensor to sense the temperature of the power die, a current sensor to sense the current going through the power die, a gate interrupt circuit to interrupt the signal provided to the power die if the sensed current is higher than a predetermined current threshold, a controller to reduce the conducting time of the die if the sensed temperature of the power die is higher than the average die temperature across the power dies of at least one switch.

A circuit comprises a first metal-oxide semiconductor, MOS, power transistor having a first gate terminal, a first drain terminal, and a first source terminal, a second MOS power transistor having a second gate terminal, a second drain terminal, and a second source terminal, and a switch connected in-between the first gate terminal and the second gate terminal and configured to selectively couple the first gate terminal and the second gate terminal.

Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.