A hot swap controller circuit includes a comparator and current control circuitry. The comparator is configured to compare voltage across a power transistor controlled by the hot swap controller circuit to a predetermined threshold voltage. The current control circuitry is coupled to the comparator. The current control circuitry is configured to limit current through the power transistor to no higher than a predetermined high current based on the voltage across the transistor being less than the predetermined threshold voltage. The current control circuitry is also configured to limit the current through the transistor to be no higher than a predetermined low current based on the voltage across the transistor being greater than the predetermined threshold voltage. The predetermined high current is greater than the predetermined low current.

Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.

Provided is a switch apparatus that provides a connection or a disconnect between an input terminal and an output terminal, including a mechanical switch section and a first semiconductor switch section that are connected in series, between the input terminal and the output terminal; a second semiconductor switch section that is connected in parallel with the mechanical switch section and the first semiconductor switch section, between the input terminal and the output terminal; and a switch control section that individually controls respective ON/OFF timings of the first semiconductor switch section and the second semiconductor switch section and an open/close timing of the mechanical switch section.

A converter comprises a first switching element and a second switching element coupled between an input power source and an output capacitor and an inductor coupled to a common node of the first switching element and the second switching element, wherein the second switching element comprises a first diode and a first switch connected in series between a first terminal and a second terminal of the second switching element and a second diode connected between the first terminal and the second terminal of the second switching element.

The invention relates to a method (200) and a control device (I) for controlling at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel for switching a total current (I_ges). The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1 . . . LHS2). An input terminal (EA) for feeding the total current (I_ges), an output terminal (AA) for discharging the total current (I_ges), and a joint control terminal (S) for receiving a joint control signal (SI) that has the state disconnect or connect are provided. The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel are connected to the input terminal (EA) at an input end and to the output terminal (AA) at the output end.

A gate drive apparatus including a switching time measurement unit that calculates a first or second delay time that is between a time at which a rising edge or a falling edge of a gate voltage is applied to the gate terminal of a switching element and a time at which the switching element is turned on or off. The gate drive apparatus further includes first and second time difference calculation units that respectively calculate first and second time differences, first and second pulse generation units that respectively generate first and second pulses having pulse widths that respectively match the first and second time differences, and first and second auxiliary switches that are configured to, upon receiving a first pulse or a second pulse, supply a source current to the gate terminal that corresponds to the first pulse, or absorb a sink current from the gate terminal that corresponds to the second pulse.

A gate drive apparatus including a switching time measurement unit that calculates a first or second delay time that is between a time at which a rising edge or a falling edge of a gate voltage is applied to the gate terminal of a switching element and a time at which the switching element is turned on or off. The gate drive apparatus further includes first and second time difference calculation units that respectively calculate first and second time differences, first and second pulse generation units that respectively generate first and second pulses having pulse widths that respectively match the first and second time differences, and first and second auxiliary switches that are configured to, upon receiving a first pulse or a second pulse, supply a source current to the gate terminal that corresponds to the first pulse, or absorb a sink current from the gate terminal that corresponds to the second pulse.

A hybrid switch apparatus includes a standard semiconductor switch and a fast semiconductor switch electrically arranged in parallel to form a joint output current path for carrying a load current. The standard switch may be a silicon (Si) MOSFET while the fast switch may be a GaN high electron mobility transistor (HEMT). A means for producing first and second gate drive signals includes a pulse former. The first gate drive signal is applied the standard switch for selectively turning the standard switch on and off. The pulse former outputs the second gate drive signal for driving the fast switch, where the pulse former generates the second gate drive signal as a switch-on pulse starting synchronously with each transition of the first gate drive signal and which generates the second gate drive signal in an OFF state in between pulses to avoid incurring a conduction loss in the fast switch.

An IC chip, a system and a method of operating the IC chip in response to an event trigger are provided. The method includes responsive to the event trigger, coupling a pin to a source of constant current to charge an external capacitor coupled to the pin and monitoring a capacitor voltage on the pin. If the magnitude of the capacitor voltage is greater than a rising threshold, detection of a falling threshold is enabled. If the magnitude of the capacitor voltage is greater than a voltage threshold, a first response is triggered and the pin is coupled to the lower rail to discharge the external capacitor. If detection of the falling threshold is enabled and the magnitude of the capacitor voltage is less than the falling threshold, the first response is also triggered.

The invention relates to a circuit assembly for protecting a unit to be operated from a supply network against overvoltage, comprising an input having a first and a second input connection, which are connected to the supply network, an output having a first and a second output connection, to which the unit to be protected can be connected, and a protection circuit, which is provided between the first and the second input connections in order to limit the voltage present at the first and the second input connections. According to the invention, the protection circuit has a power semiconductor, in particular an IGBT, wherein a series circuit consisting of a diac, i.e., a bidirectional electrode, and a Zener element is connected between the collector and the gate of the power semiconductor, wherein the sum of the Zener voltage and the diac voltage results in a clamping voltage for the power semiconductor, which lies above the voltage of the supply network and defines the protection level.