A gate drive device drives a gate of each of two semiconductor switching elements constituting upper and lower arms of a half bridge circuit. The gate drive device detects a peak value of an element voltage that is a voltage of a main terminal of one of the two semiconductor switching elements, as one semiconductor switching element, or a change rate of the element voltage during a change period in which the element voltage changes. The gate drive device determines whether an energization to the one semiconductor switching element during the change period is a forward energization in which a current flows in a forward direction or a reverse energization in which the current flows in a reverse direction.

An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.

To provide a semiconductor device signal transmission circuit for drive-control, a method of controlling a semiconductor device signal transmission circuit for drive-control, a semiconductor device, a power conversion device, and an electric system for a railway vehicle capable of preventing malfunction due to noise while speeding up or reducing loss of a switching operation. The semiconductor device signal transmission circuit for drive-control that is connected between a semiconductor device constituting an arm in a power conversion device and a drive circuit configured to drive the semiconductor device, including: an inductor; and an impedance circuit including a switch and connected in parallel with the inductor.

A radio frequency (RF) switch includes a first terminal, a second terminal, a series switch circuit, a shunt switch circuit, an inductor and a reference voltage terminal. An RF signal at the first terminal. The series switch circuit is coupled to the first terminal, the second terminal, and the shunt switch circuit. The shunt switch circuit includes a sub-switch circuit, a transistor coupled to the sub-switch circuit, and a compensation capacitor parallel-coupled to the transistor. The inductor is coupled to the shunt switch circuit and the reference voltage terminal. When the RF signal is operated in a first frequency band, the first transistor is turned on for the shunt switch circuit and the inductor to provide a first impedance. When the RF signal is operated in a second frequency band, the first transistor is turned off for the shunt switch circuit and the inductor to provide a second impedance.

A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.

A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.

A driving circuit and a driving method are provided. According to embodiments of the present disclosure, a power switch is driven by constant voltage or constant current during different time periods. The power switch is driven by using a first driving current during a Miller platform period, and the power switch is driven by using a second driving current when the Miller platform period ends, where the first driving current is less than the second driving current, so as to optimize EMI, reduce loss and improve efficiency.

A selection circuit architecture makes it possible to perform upward and/or downward transitions in sets of sequences of slow and fast phases so as at the same time to solve the problems of inductive switching noise and the problems of currents in the supply rails. This solution has multiple advantages linked to the ease of implementation and flexibility of configurations that are possible for adapting to the specific constraints when designing the circuit.