A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

Disclosed is a switch control circuit coupled between a switch control node and a voltage terminal. The switch control node is between an input circuit and a switch. The switch control circuit includes: an electronic component being turned on or off according to voltages of the switch control node and a control voltage node in a power-on state and preventing the voltage of the switch control node from being higher than a predetermined voltage in a power-off state; a control circuit outputting a control signal to the control voltage node in the power-on state and having no effective control over the voltage of the control voltage node in the power-off state; and a resistive component coupled between the control voltage node and voltage terminal. The electronic and resistive components function as at least a part of a leakage path to assist in turning off the switch in the power-off state.

A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

A circuit may include an electronic switch that has a load current path coupled between an output node and a supply node and that is configured to connect or disconnect the output node and the supply node in accordance with a drive signal. Further, the circuit includes a monitoring circuit that is configured to receive a current sense signal, which represents the load current passing through the load current path, and that is further configured to determine a protection signal based on the current sense signal, a state of the monitoring circuit, and at least one wire parameter. The wire parameter characterizes a wire that isduring operationconnected to the output node, and the protection signal is indicative of whether to disconnect the output node from supply node. Further, the circuit includes a protection circuit connected to the monitoring circuit.

Disclosed is a switch control circuit coupled between a switch control node and a voltage terminal. The switch control node is between an input circuit and a switch. The switch control circuit includes: an electronic component being turned on or off according to voltages of the switch control node and a control voltage node in a power-on state and preventing the voltage of the switch control node from being higher than a predetermined voltage in a power-off state; a control circuit outputting a control signal to the control voltage node in the power-on state and having no effective control over the voltage of the control voltage node in the power-off state; and a resistive component coupled between the control voltage node and voltage terminal. The electronic and resistive components function as at least a part of a leakage path to assist in turning off the switch in the power-off state.

A conversion circuit includes a main device including a first terminal, a second terminal and a control terminal, and a voltage control switching circuit including a first terminal configured to receive an first driving signal, a second terminal coupled to the control terminal of the main device and configured to transmit a second driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A current passing through the voltage control switching device is controlled in response to a voltage level of the reference terminal.

A diving circuit drives an output transistor according to a control signal S.sub.CTRL. The gate of the first transistor is biased. The source of the first transistor is coupled to an internal line. In the on period of the output transistor, the voltage of the internal line is applied to a control electrode of the output transistor. A voltage correction circuit controls the internal line so as to gradually lower the voltage V.sub.REGB of the internal line with time.

A diving circuit drives an output transistor according to a control signal S.sub.CTRL. The gate of the first transistor is biased. The source of the first transistor is coupled to an internal line. In the on period of the output transistor, the voltage of the internal line is applied to a control electrode of the output transistor. A voltage correction circuit controls the internal line so as to gradually lower the voltage V.sub.REGB of the internal line with time.