A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal.

A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.

A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.

Disclosed is an circuit for preventing latch-up, comprising a first transistor, a second transistor of a type opposite to that of the first transistor, and a control circuit, wherein a control terminal of the first transistor receives a first control voltage and a first terminal of the first transistor receives a first supply voltage; a control terminal of the second transistor receives a second control voltage, and is connected to a second terminal of the first transistor; a first terminal of the second transistor is connected to the control terminal of the first transistor, and a second terminal of the second transistor receives a second supply voltage. The control circuit is coupled on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage for disconnecting the path when the first control voltage and/or the second control voltage is out of a predetermined range.

A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal.

The present disclosure describes a system and method for resetting firmware in an electronic accessory, such as a wearable electronic device, without a physical reset button on the accessory. A secondary device, such as a case for the accessory, can serve as a power source that initiates the reset. The reset may be manually initiated, for example by a user pressing a button, or automatically initiated, such as by the secondary device detecting that the accessory is unresponsive. The secondary device sends a reset command to the electronic accessory through a power line connection. The power line connection may be made, for example, upon contact of the accessory with the secondary device. In some examples, the reset command may be an elevated power level. Upon receiving the reset command through the power line, the accessory completes the reset.

The present disclosure describes a system and method for resetting firmware in an electronic accessory, such as a wearable electronic device, without a physical reset button on the accessory. A secondary device, such as a case for the accessory, can serve as a power source that initiates the reset. The reset may be manually initiated, for example by a user pressing a button, or automatically initiated, such as by the secondary device detecting that the accessory is unresponsive. The secondary device sends a reset command to the electronic accessory through a power line connection. The power line connection may be made, for example, upon contact of the accessory with the secondary device. In some examples, the reset command may be an elevated power level. Upon receiving the reset command through the power line, the accessory completes the reset.

A diagnostic system for a DC-DC voltage converter having a high voltage switch, a low voltage switch, and a DC-DC voltage converter control circuit is provided. The system includes first and second tri-state buffer ICs and a microcontroller. The first tri-state buffer IC receives a first shutdown indicator voltage from the DC-DC voltage converter control circuit indicating that a first plurality of FET switches in a high side FET IC and a second plurality of FET switches in a low side FET IC have been transitioned to an open operational state. The first tri-state buffer IC outputs a second shutdown indicator voltage to the microcontroller that indicates that the first and second plurality of FET switches have been transitioned to the open operational state.

A diagnostic system for a DC-DC voltage converter having a high voltage switch, a low voltage switch, and a DC-DC voltage converter control circuit is provided. The system includes first and second tri-state buffer ICs and a microcontroller. The first tri-state buffer IC receives a first shutdown indicator voltage from the DC-DC voltage converter control circuit indicating that a first plurality of FET switches in a high side FET IC and a second plurality of FET switches in a low side FET IC have been transitioned to an open operational state. The first tri-state buffer IC outputs a second shutdown indicator voltage to the microcontroller that indicates that the first and second plurality of FET switches have been transitioned to the open operational state.

A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.