A data transmitter includes a transmitting circuit configured to transmit data, the data including alternating odd-numbered data and even-numbered data. The transmitting circuit includes a first flip flop configured to receive the odd-numbered data and generate retimed odd-numbered data, and a second flip flop configured to receive the even-numbered data and generate retimed even-numbered data. The data transmitter includes a clock transmitting circuit configured to supply a clock signal to the transmitting circuit, the clock transmitting circuit including a clock driver configured to transmit the clock signal to a receiver that receives the data.

A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.

An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.

An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

A code shift calculation circuit is provided. A first operation circuit of the code shift calculation circuit generates a first output value according to a temperature difference and a first change rate of a driving strength code to temperature. The temperature difference is a difference between a previous temperature when getting a previous ZQ command and a current temperature when getting a current ZQ command. A second operation circuit generates a second output value according to a voltage difference and a second change rate of the driving strength code to voltage. The voltage difference is a difference between a previous working voltage when getting the previous ZQ command and a current working voltage when getting the current ZQ command. A third operation circuit sums up the first output value and the second output value to generate a shift value, thereby adjusting the driving strength code calibrated by ZQ calibration.

An electronic system includes a reception device and a transmission device. The reception device generates reception data from transmission data input to a reception node and includes a termination circuit which is coupled to the reception node to perform an impedance matching operation. The transmission device generates a drive control signal from internal data based on a mode signal and drives the transmission data based on the drive control signal.