An impedance calibration circuit includes first and second calibration circuits, a switch circuit and a control circuit. The first calibration circuit is coupled to an external resistance, and generates a first voltage. The second calibration circuit generates second and third voltages. The switch circuit is coupled to the first and second calibration circuits. The switch circuit selectively provides the first, second, and third voltages to first and second nodes. The control circuit is coupled to the first and second nodes. The control circuit generates first, second, and third control signals according to voltages of the first and second nodes. In a first time interval, the switch circuit provides the first voltage to the first and second nodes. In a second time interval, the switch circuit provides the second voltage to the first and second nodes, or provides the second and third voltages respectively to the first and second nodes.

An electronic system includes a reception device and a transmission device. The reception device generates reception data from transmission data input to a reception node and includes a termination circuit which is coupled to the reception node to perform an impedance matching operation. The transmission device generates a drive control signal from internal data based on a mode signal and drives the transmission data based on the drive control signal.

An impedance calibration circuit is provided. The impedance calibration circuit includes a first calibration circuit, a second calibration circuit and a control circuit. The first calibration circuit is adapted to be coupled to an external resistor through a calibration pad, and generate a first voltage according to a first control signal and a resistance value of the external resistor. The second calibration circuit generates a second voltage according to the first control signal and a second control signal. The control circuit is configured to compare the first voltage and a reference voltage to obtain a first comparison result, and compare the first voltage and the second voltage to obtain a second comparison result, and generate the first control signal according to the first comparison result, and generate the second control signal according to the second comparison result.

A switching circuit includes a first transmission terminal, a second transmission terminal, a third transmission terminal, and a variable impedance circuit. The first and the second transmission terminals coupled to a common node form a first transmission path. The third transmission terminal coupled to the common node forms a second transmission path with the first transmission terminal. The variable impedance circuit has a first terminal coupled between the common node and the third transmission terminal, and a second terminal coupled to a first reference potential terminal. When the first transmission path transmits a first signal, a first frequency bandwidth range provided by the variable impedance circuit is determined according to a first frequency of the first signal so that the variable impedance circuit provides low impedance in the first frequency bandwidth range, and the first frequency bandwidth range covers the first frequency.

A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

An impedance adjustment circuit is connected in parallel with a bias current output end of a bias circuit. The bias circuit is configured to provide bias current to a first circuit unit. The impedance adjustment circuit is configured to adjust source impedance of the first circuit unit.

Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a single-ended termination circuit with a first via configuration, a Thevenin termination circuit with a second via configuration, and/or a differential termination circuit with a third configuration.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.