Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

A semiconductor device according to an embodiment of the present disclosure includes an output driver including a first variable resistor element, a replica circuit including a second variable resistor element and having the same configuration as the output driver, a first wiring line coupled to an output end of the replica circuit; a second wiring line electrically coupled to a first external terminal; and a comparator that compares a voltage of the first wiring line with a voltage of the second wiring line.

Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

An electrical system includes an integrated circuit device including input/output (I/O) pins, a reset circuit, and an I/O circuit. The I/O circuit is operably coupled to the I/O pins. The I/O circuit is configured to selectively operate the I/O pins in an electrically floating state responsive to a system reset signal transmitted by the reset circuit. The I/O circuit is further configured to selectively operate the I/O pins in the electrically floating state responsive to a signal provided by a timer circuit independently from the reset circuit.

In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.

An output buffer circuit includes an output terminal, a transistor, and a resistor. The transistor includes a first terminal coupled to the output terminal, a second terminal coupled to a ground rail, and a third terminal coupled to an output signal source. The resistor includes a first terminal coupled to a fourth terminal of the transistor, and a second terminal coupled to the ground rail.

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.