Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

A code shift calculation circuit is provided. A first operation circuit of the code shift calculation circuit generates a first output value according to a temperature difference and a first change rate of a driving strength code to temperature. The temperature difference is a difference between a previous temperature when getting a previous ZQ command and a current temperature when getting a current ZQ command. A second operation circuit generates a second output value according to a voltage difference and a second change rate of the driving strength code to voltage. The voltage difference is a difference between a previous working voltage when getting the previous ZQ command and a current working voltage when getting the current ZQ command. A third operation circuit sums up the first output value and the second output value to generate a shift value, thereby adjusting the driving strength code calibrated by ZQ calibration.

A driver for transmitting multi-level signals on a multi-wire bus is described that includes at least one current source connected to a transmission line, each current source selectively enabled to source current to the transmission line to drive a line voltage above a termination voltage of a termination voltage source connected to the transmission line via a termination impedance element, wherein each of the at least one current sources has an output impedance different than a characteristic impedance of the transmission line, and at least one current sink connected to the transmission line, each current sink selectively enabled to sink current from the transmission line to drive a line voltage below the termination voltage, each of the at least one current sinks having an output impedance different than the characteristic impedance of the transmission line.

In a testing device, a method for implementing automatic RF port testing. The method includes attaching a device under test having a plurality of RF pins to a load board, dynamically tuning a plurality of RF ports of the load board to the plurality of RF pins, and automatically matching the plurality of RF ports to the plurality of RF pins with respect to impedance. The method further includes implementing an RF port testing process on the device under test.

An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.

A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.

An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

An impedance calibration circuit includes a first reference resistor electrically coupled to a calibration pad, a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode, and a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code.

A communication device, a communication system and an operation method thereof are provided. The communication device includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is configured to execute a first communication protocol to work with the MCU so as to communicate with another communication device in a first period, and meanwhile the FPGA is programmed with a second communication protocol by the MCU in the same first period. The FPGA is controlled by a switch pulse output from the MCU to terminate the first period, and switched from the first communication protocol to the second communication protocol, and then executes the second communication protocol to work with the MCU so as to communicate with the another communication device in a second period.