A system in a package (SIP) has a first die with a first internal voltage level, first die-to-die output circuitry, first die-to-die input circuitry, and first internal logic and a second die with a second internal voltage level, second die-to-die output circuitry, second die-to-die input circuitry, and second internal logic. A first signal is provided to the second internal logic via the first die-to-die output circuitry and the second die-to-die input circuitry, wherein each of the first die-to-die output circuitry and second die-to-die input circuitry selectively level shift the first signal based on the first and second internal voltage levels. A second signal is provided to the first internal logic via the second die-to-die output circuitry and the first die-to-die input circuitry, wherein each of the second die-to-die output circuitry and first die-to-die input circuitry selectively level shift the second signal based on the first and second internal voltage levels.

A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to traverse a link list of connected components forming an object in an image being processed in a machine vision system. The link list may comprise object IDs and link pointers for each component of the object. The link pointers generally identify links between each component from a current leaf component to a root component of the object. Each of the connected components may comprise one or more pixels of the image belonging to the object. The second circuit may be configured to modify at least the link pointer associated with the current leaf component to point to the root component instead of a next component between the current leaf component and the root component by generating a control signal to control replacement of at least an object ID of a next connected leaf component in the link pointer of the current leaf component with the object ID of the root component.

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

A circuit can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using one or more JJ-based current sources.

Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.