Apparatus and method for actively mitigating coherent errors by modifying an original quantum circuit, inserting Clifford gate operations at intermediate stages. Embodiments of the apparatus and method may perform CGI statically, at the compiling stage, and/or dynamically, at the control processing stage. The insertion of Clifford gates takes advantage of the symmetries in a quantum circuit and actively cancels coherent errors, maintaining the quantum processor in a state as close as possible to the original tune-up environment.

A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.

A method for controlling an electrical switch using a driver waveform, wherein the driver waveform comprises: a first time period, T.sub.1, associated with a first current, I.sub.G_high; a second time period, T.sub.2, associated with a second current, I.sub.G_low; wherein: the first current of the driver waveform, I.sub.G_high, is larger than the second current of the driver waveform, I.sub.G_low; and the first time period, T.sub.1, has a first duration and the second time period, T.sub.2, has a second duration. The method comprising: determining an optimised first duration by repeatedly modifying the first duration until an overshoot in an output waveform generated by switching the electrical switch using the driver waveform is less than a threshold; determining an optimised second duration based on the optimised first duration; and switching the electrical switch using the optimised first duration and the optimised second duration.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A switch assembly configured to determine when input received from a switch is caused by proper actuation of the switch and should be accepted, or is caused instead by a fault in the switch or in the intervening circuitry and should be ignored and/or reported. The switch assembly optionally includes a logic circuit that is electrically connected to the switch. The logic circuit may provide power to the switch, for example, as a time varying signal, which may then be presented to the logic circuit as input when the switch is properly actuated. The logic circuit may then compare the input from the switch with the signal sent to the switch to determine if a fault is present, or if the switch is operating properly.

A switch assembly configured to determine when input received from a switch is caused by proper actuation of the switch and should be accepted, or is caused instead by a fault in the switch or in the intervening circuitry and should be ignored and/or reported. The switch assembly optionally includes a logic circuit that is electrically connected to the switch. The logic circuit may provide power to the switch, for example, as a time varying signal, which may then be presented to the logic circuit as input when the switch is properly actuated. The logic circuit may then compare the input from the switch with the signal sent to the switch to determine if a fault is present, or if the switch is operating properly.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. The first transistor is controlled by a enable signal. The second transistor is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit generates the second control signal according to the first control signal and the enable signal.