An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

An integrated circuit according to one or more embodiments may include a terminal to which an impedance element and a power supply having a predetermined potential can be connected. The integrated circuit may be configured to change a potential of one of electrodes of the impedance element connected to the terminal, detect a change in electrical characteristics of the terminal based on characteristics of the impedance element when the potential of the one electrode of the impedance element is changed, to determine a setting condition among a plurality of setting conditions that are used for an operation of the integrated circuit, store the setting condition in a storage, and use the setting condition stored in the storage for the operation of the integrated circuit.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

A reconfigurable and machine learning resilient on-chip cryptography for graphene-based devices can be configured to utilize inherent disorders associated with the carrier transport in grain boundary dominated graphene field effect transistors (GFETs). For instance, a method can be configured to model a GFET as one or more physically unclonable functions (PUFs). A GFET PUF can also be reconfigured in a way that does not involve any physical intervention and/or integration of additional hardware components. A GFET PUF can be designed to operate with ultra-low power and can be configured to be robust and reliable against variation in temperature and supply voltage in some embodiments.

A reconfigurable and machine learning resilient on-chip cryptography for graphene-based devices can be configured to utilize inherent disorders associated with the carrier transport in grain boundary dominated graphene field effect transistors (GFETs). For instance, a method can be configured to model a GFET as one or more physically unclonable functions (PUFs). A GFET PUF can also be reconfigured in a way that does not involve any physical intervention and/or integration of additional hardware components. A GFET PUF can be designed to operate with ultra-low power and can be configured to be robust and reliable against variation in temperature and supply voltage in some embodiments.

In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to generate a second output; and a second sub-circuit comprising a connecting p-type transistor arrangement and a connecting n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other through the second sub-circuit.