An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Disclosed is a switching circuit including an input terminal, a switching terminal, a grounding terminal, a bootstrap terminal, a high-side transistor connected between the input terminal and the switching terminal, a low-side transistor connected between the switching terminal and the grounding terminal, a bootstrap capacitor connected between the switching terminal and the bootstrap terminal, a bootstrap switch connected between a constant voltage line and the bootstrap terminal, and a driver circuit configured to turn on the bootstrap switch in a period of time in which the low-side transistor is on and to turn off the bootstrap switch in a period of time in which the low-side transistor is off. The bootstrap switch includes two P-channel metal oxide semiconductor transistors connected in anti-series with each other between the constant voltage line and the bootstrap terminal.

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10.sup.−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

A strong and weak hybrid PUF circuit comprises N switch units and an arbiter. Each switch unit consists of two delay modules and two 2:1 multiplexers. The N switch units constitute two completely symmetrical delay paths. Each delay module consists of six stages of delay cells. During the operating process, a transmission signal selects a turn-on path of the corresponding 2:1 multiplexers according to activation signals; the switch units in the PUF circuit are in a valid state (if the delay modules are turned on) or in an invalid state (if the delay modules are not turned on) according to whether the delay modules are turned during the operating process; and the strong and weak hybrid PUF circuit can be flexibly configured to be of two different types (a strong PUF circuit and a weak PUF circuit) according to changes of the Hamming weight of input activation signals.

A strong and weak hybrid PUF circuit comprises N switch units and an arbiter. Each switch unit consists of two delay modules and two 2:1 multiplexers. The N switch units constitute two completely symmetrical delay paths. Each delay module consists of six stages of delay cells. During the operating process, a transmission signal selects a turn-on path of the corresponding 2:1 multiplexers according to activation signals; the switch units in the PUF circuit are in a valid state (if the delay modules are turned on) or in an invalid state (if the delay modules are not turned on) according to whether the delay modules are turned during the operating process; and the strong and weak hybrid PUF circuit can be flexibly configured to be of two different types (a strong PUF circuit and a weak PUF circuit) according to changes of the Hamming weight of input activation signals.