The present invention relates to an ultrasound beam quality test apparatus and methods of use. In this regard, fetal heart rate (FHR) transducer is placed for test and interconnected with fetal monitors. Phantoms of different heights can be placed on the FHR transducer. A computer system includes a beam control circuit. A plurality of hydrophone piezo-electric crystal (PZT) discs are placed on top of the phantom and interconnected with the beam control circuit. The computer system analyzes the ultrasound beam quality, of the FHR transducer, as it passes through the phantom. The beam control circuit can also control the oscillating motion of a metal plate to simulate a fetal heart beat by way of a linear actuator. The FHR transducer registered heartbeat, by way of the fetal monitor, is then compared to the simulated fetal heart beat to determine if the FHR transducer is working correctly.

A safety switching device for fail-safely disconnecting an electrical load has an input part for receiving a safety-relevant input signal, a logic part for processing the at least one safety-relevant input signal, and an output part. The output part has a relay coil and four relay contacts. The first and second relay contacts are arranged electrically in series with one another. The third and fourth relay contacts are also arranged electrically in series with one another. The first and the third relay contacts are mechanically coupled to each other and form a first group of positively driven relay contacts. The second and the fourth relay contacts are mechanically coupled to each other and form a second group of positively driven relay contacts. The logic part redundantly controls the first and the second groups of positively driven relay contacts to selectively allow, or to interrupt in a fail-safe manner, a current flow to the electrical load, depending on the safety-relevant input signal. The relay coil is electromagnetically coupled to the first and second groups of positively driven relay contacts so that the logic part can control the relay contacts together via a single relay coil.

A tristate output buffer includes a first branch with a first buffer, and a second branch with a second buffer. The first buffer includes a supply port, a ground port, an output port, two switchable semiconductor elements of a first type, and two switchable semiconductor elements of a second type. Switching behavior of the switchable semiconductor elements of the first type differs from switching behavior of the switchable semiconductor elements of the second type. The two switchable semiconductor elements of the first type are connected in series and are between the supply port and the output port such that they can be put in a conductive state independent of each other. The two switchable semiconductor elements of the second type are connected in series and are between the ground port and the output port such that they can be put in a conductive state independent of each other.

A tristate output buffer includes a first branch with a first buffer, and a second branch with a second buffer. The first buffer includes a supply port, a ground port, an output port, two switchable semiconductor elements of a first type, and two switchable semiconductor elements of a second type. Switching behavior of the switchable semiconductor elements of the first type differs from switching behavior of the switchable semiconductor elements of the second type. The two switchable semiconductor elements of the first type are connected in series and are between the supply port and the output port such that they can be put in a conductive state independent of each other. The two switchable semiconductor elements of the second type are connected in series and are between the ground port and the output port such that they can be put in a conductive state independent of each other.

A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit.

According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

A scannable data synchronizer including an input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives the data nodes to opposite logic states in response to an asynchronous input data signal in a normal mode and in response to scan data in a scan test mode. Each pass gate is coupled between one of the data nodes and a corresponding one of the capture nodes, and each has at least one control terminal. The inverters are cross-coupled between the second capture nodes. The gate controller can keep the pass gates at least partially open during a metastable condition of the capture nodes, and can close the pass gates when both capture nodes stabilize to opposite logic states. In the scan test mode, the scan data is used to test the latch or register functions of the scannable data synchronizer.

A device includes a sensor and an actuator. The sensor has a receiving circuit with a sensor and a detector, as well as a computer connected to the detector. The sensor cooperates with the actuator to generate a first receiving circuit signal during a normal operation when a switching distance between the sensor and the actuator is undershot. The detector generates a first output signal as a function of the first receiving circuit signal, and to transmit transmits the first output signal to the computer. The receiving circuit includes a signal emulator and a switch-over element. The signal emulator generates a second receiving circuit signal during a test operation. The detector generates a second output signal as a function of the second receiving circuit signal and transmits the second output signal to the computer. The device can repeatedly switch between normal operation and test operation.

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.