A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path. Said microelectronic circuit is configured to freeze a first digital value stored in said first register circuit (301) for a time during which the change generated through said controllable data event injection point (503) propagates to said first register circuit.

Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

A digital input circuit for receiving digital input signals of at least one signal generator comprises first and second subcircuits. Each subcircuit includes a digital input to receive a digital input signal and a threshold value element to determine a logic state of the subcircuit. Each subcircuit adopts a first state in response to its digital input signal reaching or falling below a lower threshold value and adopts a second state in response to its digital input signal reaching or exceeding an upper threshold value. The digital input circuit further comprises a combined test and current increasing apparatus to generate a driving signal such that a function test of both the first and second subcircuits is conducted simultaneously with the driving signal and an input current of the digital inputs is increased.

An active power blocking circuit in series with a squib. The active power blocking circuit may include a logic circuit, a first switch, a second switch, and an amplifier. The first switch may have a first side connected to a positive connection and a second side connected to a negative connection. The second switch may have a first side connected to the positive connection and a second side connected to the negative connection through a diode. The amplifier may be connected the second side of the second switch and the output of the amplifier may be connected to the logic circuit.

The invention relates to a safety-related switching device (10) which is equipped with an electromagnetic coil (12), a control unit (20) and a first switching means (22). The first switching means (22) is designed to activate and deactivate the electromagnetic coil (12). Moreover, the first switching means (22) is designed to receive a coil control signal (24), a monitoring signal (32) and a first higher-level control signal (26). The safety-related switching device (10) also has a receiver unit (40) for receiving an external control signal (29). The receiver unit (40) is designed to generate the first higher-level control signal (26) and a second higher-level control signal (28) from the external control signal (29). The control unit (20) is designed to receive the second higher-level control signal (28).

A monitoring device includes a monitoring part configured to detect an abnormality of a monitoring target, a self-diagnosis part configured to diagnose whether or not the monitoring part operates normally during a period from a startup time point of a power supply to an elapse time point at which a reset release waiting time elapses, and a reset control part configured to release a reset of a reset output signal on or after the elapse time point.

A monitoring device includes a monitoring part configured to detect an abnormality of a monitoring target, a self-diagnosis part configured to diagnose whether or not the monitoring part operates normally during a period from a startup time point of a power supply to an elapse time point at which a reset release waiting time elapses, and a reset control part configured to release a reset of a reset output signal on or after the elapse time point.