A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.

One example discloses a power application circuit, including: a first power application circuit, configured to receive an enable signal and a first voltage; wherein the first power application circuit is configured to output the first voltage at a first current after a first delay from when the enable signal is received; and a second power application circuit, configured to receive the enable signal and a second voltage; wherein the second power application circuit is configured to output the second voltage at a second current after a second delay from when the enable signal is received.

A low voltage differential signaling (LVDS) driver circuit, system, apparatus, and methodology are provided for controlling switching components in a primary current stage and a pre-emphasis current stage with an adaptive pre-emphasis gain tuning hardware control circuit arranged to provide control signals for periodically tuning a pre-emphasis gain setting for the secondary pre-emphasis current stage by selecting an optimum pre-emphasis gain setting from a plurality of pre-emphasis gain setting which minimizes an inter-symbol interference (ISI) jitter measure for the LVDS driver circuit.

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

A level-shifter is provided with a first transistor and a second transistor. The first transistor functions to discharge an internal node responsive to an assertion of an inverted input signal to a first power supply voltage. A second transistor functions to discharge an inverted level-shifter output signal responsive to an assertion of an input signal to the first power supply voltage. An inverter inverts the inverted level-shifter output signal to form a level-shifter output signal that is asserted to a second power supply voltage responsive to the assertion of the input signal.

A fast switching time is highly desired in the design of mobile handsets. The limiting factor in the switching time is the resistor through which bias is applied to amplifiers used within such handsets. Bypassing the bias resistor when amplifiers are transitioning is a way to improve switching time without compromising the RF performance. Methods and devices to generate short pulses without relying on a continuously running clock and used to bypass bias resistors are described.

A fast switching time is highly desired in the design of mobile handsets. The limiting factor in the switching time is the resistor through which bias is applied to amplifiers used within such handsets. Bypassing the bias resistor when amplifiers are transitioning is a way to improve switching time without compromising the RF performance. Methods and devices to generate short pulses without relying on a continuously running clock and used to bypass bias resistors are described.

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.