A current booster circuit, which can be coupled between a gate driver and a power switch, includes controlled current sources and current sensors to provide a scaled copy of the booster input current at the booster output while operating in a current-gain mode during on-to-off or off-to-on switching periods. During switched-on or switched-off periods, the booster can pull the output to the high or low rail, respectively, through low-impedance circuitry to hold the switch on or off. A voltage and/or current feedback path between the booster output and the booster input permits the booster to control the voltage input during switching operation. The current booster devices and methods can be compatible with both smart and conventional gate drivers of either the voltage-driven or current-driven variety.

Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

A semiconductor switch control circuit includes: a pulse signal generating part configured to generate a pulse signal which becomes a time reference for performing an ON/OFF control of a semiconductor switch; a drive current generating part configured to generate a drive current based on the pulse signal which the pulse signal generating part generates and to supply the drive current to a gate electrode of the semiconductor switch; a current detecting part configured to detect a drain current or a source current of the semiconductor switch; and a drive current control part configured to have a function of controlling a drive current which the drive current generating part generates based on the pulse signal which the pulse signal generating part generates and the current which the current detecting part detects.

A semiconductor switch control circuit includes: a pulse signal generating part configured to generate a pulse signal which becomes a time reference for performing an ON/OFF control of a semiconductor switch; a drive current generating part configured to generate a drive current based on the pulse signal which the pulse signal generating part generates and to supply the drive current to a gate electrode of the semiconductor switch; a current detecting part configured to detect a drain current or a source current of the semiconductor switch; and a drive current control part configured to have a function of controlling a drive current which the drive current generating part generates based on the pulse signal which the pulse signal generating part generates and the current which the current detecting part detects.

A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

An apparatus and a method are provided for generating and transmitting one or more band segmented bootstrap signals. For example, a transmitter may be configured to generate a plurality of sequence numbers and apply cyclic shift to each of the plurality of sequence number. The transmitter is further configured to map each of the shifted sequence numbers to at least one frequency domain subcarrier of a plurality of frequency domain subcarriers, and translate each subcarrier of the plurality of subcarriers to a time domain sequence. Each subcarrier of the plurality of subcarriers may be shifted with respect to other subcarriers of the plurality of subcarriers, thereby aligning each segment of the band segmented bootstrap signals next to each other in the frequency domain.

An apparatus and a method are provided for generating and transmitting one or more band segmented bootstrap signals. For example, a transmitter may be configured to generate a plurality of sequence numbers and apply cyclic shift to each of the plurality of sequence number. The transmitter is further configured to map each of the shifted sequence numbers to at least one frequency domain subcarrier of a plurality of frequency domain subcarriers, and translate each subcarrier of the plurality of subcarriers to a time domain sequence. Each subcarrier of the plurality of subcarriers may be shifted with respect to other subcarriers of the plurality of subcarriers, thereby aligning each segment of the band segmented bootstrap signals next to each other in the frequency domain.