Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

A method of generating a randomized benchmarking protocol includes providing a randomly generated plurality of Hadamard gates; applying the Hadamard gates to a plurality of qubits; and generating randomly a plurality of Hadamard-free Clifford circuits. Each of the plurality of Hadamard-free Clifford circuits is generated by at least randomly generating a uniformly distributed phase (P) gate, and randomly generating a uniformly distributed linear Boolean invertible matrix of conditional NOT (CNOT) gate, and combining the P and CNOT gates to form each of the plurality of Hadamard-free Clifford circuits. The method also includes combining each of the plurality of Hadamard-free Clifford circuits with corresponding each of the plurality of Hadamard gates to form a sequence of alternating Hadamard-free Clifford-Hadamard pairs circuit to form the randomized benchmarking protocol; and measuring noise in a quantum mechanical processor using the randomized benchmarking protocol.

A method of generating a randomized benchmarking protocol includes providing a randomly generated plurality of Hadamard gates; applying the Hadamard gates to a plurality of qubits; and generating randomly a plurality of Hadamard-free Clifford circuits. Each of the plurality of Hadamard-free Clifford circuits is generated by at least randomly generating a uniformly distributed phase (P) gate, and randomly generating a uniformly distributed linear Boolean invertible matrix of conditional NOT (CNOT) gate, and combining the P and CNOT gates to form each of the plurality of Hadamard-free Clifford circuits. The method also includes combining each of the plurality of Hadamard-free Clifford circuits with corresponding each of the plurality of Hadamard gates to form a sequence of alternating Hadamard-free Clifford-Hadamard pairs circuit to form the randomized benchmarking protocol; and measuring noise in a quantum mechanical processor using the randomized benchmarking protocol.

Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal. However, while each unit cell may be generally the same, there may be variations such as non-linearity or noise in the analog output depending on which unit cells are activated for a given digital signal value. For example, as additional unit cells are activated for increased values of the analog signal, the fill order in which the unit cells are activated may affect the linearity/noise of the DAC. The decision units may be programmable to select which branches of the fractal DAC to activate, changing the fill order based on a fill-selection signal. The fill order may be set by a fill controller via the fill-selection signal to account for manufacturing variations, gradients in the supply voltage, output line routing, and/or environmental factors such as temperature.

An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.