Patent classifications
H03K19/20
FLOATING POINT FUSED MULTIPLY ADD WITH MERGED 2'S COMPLEMENT AND ROUNDING
A method includes receiving an unrounded mantissa value and a round bit associated with the unrounded mantissa value. The method also includes receiving a 2's complement signal that indicates whether the unrounded mantissa value results from a 1's complement operation. The method includes incrementing the unrounded mantissa value to provide an incremented value. The unrounded mantissa value is a non-incremented value. The method further includes providing one of the incremented value or non-incremented value as a rounded mantissa value responsive to the 2's complement signal.
Inverted integrated circuit and method of forming the same
An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.
Inverted integrated circuit and method of forming the same
An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.
CONTROL CIRCUIT, METHOD AND SYSTEM
A control circuit including a quadrature encoder circuit, a counter circuit, and a cutoff circuit is provided. The quadrature encoder circuit generates a first edge signal and a first direction signal according to a first external signal and a second external signal. The counter circuit performs a counting operation according to the first edge signal and the first direction signal. In response to the timer signal being enabled, the cutoff circuit prevents the first edge signal and the first direction signal from entering the counter circuit and provides a second edge signal and a second direction signal to the counter circuit so that the counter circuit performs the counting operation according to the second edge signal and the second direction signal.
CONTROL CIRCUIT, METHOD AND SYSTEM
A control circuit including a quadrature encoder circuit, a counter circuit, and a cutoff circuit is provided. The quadrature encoder circuit generates a first edge signal and a first direction signal according to a first external signal and a second external signal. The counter circuit performs a counting operation according to the first edge signal and the first direction signal. In response to the timer signal being enabled, the cutoff circuit prevents the first edge signal and the first direction signal from entering the counter circuit and provides a second edge signal and a second direction signal to the counter circuit so that the counter circuit performs the counting operation according to the second edge signal and the second direction signal.
Multiple location electrical control system with synchronizing buttons
An electrical control system which controls an electrical device from two or more locations with independent control function, the system including a wall adapter having a first integrated circuit board, a first enclosure, and a second enclosure. The first enclosure includes a first push button, a first synchronizing push button, and a second IC board electrically connected to the wall adapter; and the second enclosure includes a second push button, a second synchronizing push button, and a third IC board. Each of the wall switch, the first synchronizing push button, and the second synchronizing push button is a system power control button and part of a synchronizing circuit that synchronizes the electrical control system to default system power controls upon being pressed by a user. Each of the first and second push buttons is a local button that controls a respective controlled receptable of a respective enclosure.
Multiple location electrical control system with synchronizing buttons
An electrical control system which controls an electrical device from two or more locations with independent control function, the system including a wall adapter having a first integrated circuit board, a first enclosure, and a second enclosure. The first enclosure includes a first push button, a first synchronizing push button, and a second IC board electrically connected to the wall adapter; and the second enclosure includes a second push button, a second synchronizing push button, and a third IC board. Each of the wall switch, the first synchronizing push button, and the second synchronizing push button is a system power control button and part of a synchronizing circuit that synchronizes the electrical control system to default system power controls upon being pressed by a user. Each of the first and second push buttons is a local button that controls a respective controlled receptable of a respective enclosure.
Interrupt controller and method of managing an interrupt controller
In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
Interrupt controller and method of managing an interrupt controller
In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
Memory circuit arrangement for accurate and secure read
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.