Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include receiving, at the MMD, an input signal at a first frequency. The method may also include generating, via the MMD, an output signal at a second, lower frequency based on a divisor value. Further, the method may include receiving, at the MMD, an integer value. Moreover, the method may include setting the divisor value equal to the integer value in response to a current state of the MMD matching a common state for the MMD, wherein the MMD is configured to enter the common state regardless of the divisor value.

A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.

A delay measurement apparatus for measuring a delay unit comprising: a clock; clock counter; a digital signal source that is uncorrelated with the clock; a first detector arranged to detect transitions of the digital signal entering the delay unit; a first accumulator arranged to accumulate the current clock counter value based on the output of the first detector; a second detector arranged to detect transitions of the digital signal exiting the delay unit; a second accumulator arranged to accumulate the current clock counter value based on the output of the second detector; a measurement counter arranged to count the number of transitions of the digital signal passing through the delay unit; and a calculation device arranged to calculate an average number of clock cycles that elapse while a transition of the digital signal passes through the delay unit based on the first accumulator, the second accumulator and the measurement counter.

A delay measurement apparatus for measuring a delay unit comprising: a clock; clock counter; a digital signal source that is uncorrelated with the clock; a first detector arranged to detect transitions of the digital signal entering the delay unit; a first accumulator arranged to accumulate the current clock counter value based on the output of the first detector; a second detector arranged to detect transitions of the digital signal exiting the delay unit; a second accumulator arranged to accumulate the current clock counter value based on the output of the second detector; a measurement counter arranged to count the number of transitions of the digital signal passing through the delay unit; and a calculation device arranged to calculate an average number of clock cycles that elapse while a transition of the digital signal passes through the delay unit based on the first accumulator, the second accumulator and the measurement counter.

The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wiring, and a case where it is preferable to connect the common signal terminals or the power supply terminals by circuits insulated from each other. The counter unit (10) is provided with a switching unit (15) that performs switching between a non-insulated circuit (16) that connects a plurality of common signal terminals (COMA, COMB, COMC) and/or a plurality of power supply terminals (IOV, IOG) by common wiring, and an insulated circuit (17) that connects the plurality of common signal terminals and/or the plurality of power supply terminals by circuits insulated from each other.

The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wiring, and a case where it is preferable to connect the common signal terminals or the power supply terminals by circuits insulated from each other. The counter unit (10) is provided with a switching unit (15) that performs switching between a non-insulated circuit (16) that connects a plurality of common signal terminals (COMA, COMB, COMC) and/or a plurality of power supply terminals (IOV, IOG) by common wiring, and an insulated circuit (17) that connects the plurality of common signal terminals and/or the plurality of power supply terminals by circuits insulated from each other.

Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

A fractional divider is described herein which effectively performs an integer division followed by phase shifting, pulse swallowing, and/or multiplexing to realize a fractional divisor. The fractional divider divides an input clocking signal by a first integer divisor in a first mode of operation or by a second integer divisor in a second mode of operation to provide a first phase of a divided digital signal. Thereafter, the fractional divider shifts the first phase of the divided digital signal to provide a second phase of the divided digital signal in the first and second modes of operation. Finally, the fractional divider synchronizes an output clocking signal to the first phase of the divided digital signal and the second phase of the divided digital signal in the first and second modes of operation.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

A circuit system for controlling an electrical consumer, the circuit system including an up-down counter, and the circuit system being configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter. The circuit system includes a controllable clock divider circuit, with the aid of which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer.