The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.

According to one aspect of embodiments, a driver circuit having an overcurrent protection function includes a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal for controlling turning ON and OFF of the output transistor that supplies output current to a load; and a control circuit that generates a signal indicating an overcurrent state when a count value of an overcurrent detecting signal exceeds a predetermined number, which indicates that a value of an output current of the output transistor within the predetermined time interval exceeds a predetermined threshold value.

According to one aspect of embodiments, a driver circuit having an overcurrent protection function includes a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal for controlling turning ON and OFF of the output transistor that supplies output current to a load; and a control circuit that generates a signal indicating an overcurrent state when a count value of an overcurrent detecting signal exceeds a predetermined number, which indicates that a value of an output current of the output transistor within the predetermined time interval exceeds a predetermined threshold value.

A signal source is described. The signal source comprises a signal generator, a first frequency divider and a second frequency divider. The first and the second frequency divider are each connected to the signal generator. The signal generator is configured to generate a source signal having a source frequency and to selectively forward the source signal to at least one of the first frequency divider and the second frequency divider. The first frequency divider is established as an integer frequency divider and is configured to generate a first output signal from the source signal. The second frequency divider is different from the first frequency divider and is configured to generate a second output signal from the source signal, wherein a phase noise of the second output signal is considerably lower than a phase noise of the first output signal. Moreover, a test system and a method for testing a device under test are described.

A signal source is described. The signal source comprises a signal generator, a first frequency divider and a second frequency divider. The first and the second frequency divider are each connected to the signal generator. The signal generator is configured to generate a source signal having a source frequency and to selectively forward the source signal to at least one of the first frequency divider and the second frequency divider. The first frequency divider is established as an integer frequency divider and is configured to generate a first output signal from the source signal. The second frequency divider is different from the first frequency divider and is configured to generate a second output signal from the source signal, wherein a phase noise of the second output signal is considerably lower than a phase noise of the first output signal. Moreover, a test system and a method for testing a device under test are described.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.

An LO clock signal generator includes a fundamental mixer for mixing a source clock signal with a divided version of the source clock signal. The LO clock signal generator also includes a harmonic mixer for mixing the source clock signal with a third harmonic of a divided version of the source clock signal.

In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.