A frequency measurement apparatus includes: a measurement period setting circuit that sets a measurement period based on a reference clock signal; a first counter circuit that counts the number of pulses of the reference clock signal in a period based on an input signal during the measurement period; a second counter circuit that counts the number of pulses of the input signal during the measurement period; a first frequency calculation circuit that calculates a first frequency; a second frequency calculation circuit that calculates a second frequency; and a frequency selection circuit that selects the first frequency or the second frequency as a frequency of the input signal.

A frequency measurement apparatus includes: a measurement period setting circuit that sets a measurement period based on a reference clock signal; a first counter circuit that counts the number of pulses of the reference clock signal in a period based on an input signal during the measurement period; a second counter circuit that counts the number of pulses of the input signal during the measurement period; a first frequency calculation circuit that calculates a first frequency; a second frequency calculation circuit that calculates a second frequency; and a frequency selection circuit that selects the first frequency or the second frequency as a frequency of the input signal.

A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.

A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.

A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

The present invention provides a pressure detection circuit including an oscillator unit, configured to output an oscillation signal as a count clock signal of a counter unit; and the counter unit, connected to the oscillator unit and configured to acquire a frequency of the oscillation signal and count. The pressure detection circuit further includes a comparator unit, connected to the counter unit, and configured to detect a voltage variation obtained by a pressure conversion, and send a signal to control the counter unit to count or stop counting; a voltage converter unit, connected to one input terminal of the comparator unit, and configured to supply a fixed or variable comparable voltage to the comparator unit; a constant current source charging unit, connected to the other input terminal of the comparator unit, and configured to supply a linearly and gradually increased comparison voltage to the comparator unit; a charge/discharge control unit, connected to the constant current source charging unit, and configured to control the constant current source charging unit to charge or discharge, such that the comparable voltage output by the voltage converter unit is compared to cause an output terminal of the comparator unit to enable counting of the counter unit; wherein the oscillator unit or the voltage converter unit further includes a pressure acquiring unit, as a component of the voltage converter unit or the oscillator unit, configured to convert a pressure into a variation of the comparable voltage or the frequency of the oscillation signal. The invention also provides a pressure input device pressure detection device. The invention has the technical effects of high sensitivity and resolution, power saving, and wide applicability.

The present invention provides a pressure detection circuit including an oscillator unit, configured to output an oscillation signal as a count clock signal of a counter unit; and the counter unit, connected to the oscillator unit and configured to acquire a frequency of the oscillation signal and count. The pressure detection circuit further includes a comparator unit, connected to the counter unit, and configured to detect a voltage variation obtained by a pressure conversion, and send a signal to control the counter unit to count or stop counting; a voltage converter unit, connected to one input terminal of the comparator unit, and configured to supply a fixed or variable comparable voltage to the comparator unit; a constant current source charging unit, connected to the other input terminal of the comparator unit, and configured to supply a linearly and gradually increased comparison voltage to the comparator unit; a charge/discharge control unit, connected to the constant current source charging unit, and configured to control the constant current source charging unit to charge or discharge, such that the comparable voltage output by the voltage converter unit is compared to cause an output terminal of the comparator unit to enable counting of the counter unit; wherein the oscillator unit or the voltage converter unit further includes a pressure acquiring unit, as a component of the voltage converter unit or the oscillator unit, configured to convert a pressure into a variation of the comparable voltage or the frequency of the oscillation signal. The invention also provides a pressure input device pressure detection device. The invention has the technical effects of high sensitivity and resolution, power saving, and wide applicability.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.