A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

A system is provided for dynamically reconfiguring clock output signals, without clock loss and glitches. The system includes an oscillator generating a clock input signal, first and second dynamic reconfigurable clock dividers, an AND logic gate and an interface. The first and second dynamic reconfigurable clock dividers include counters that output first and second clock output signals having multiple periodic cycles, respectively, and cycle complete signals in response to completion of each periodic cycle. The AND logic gate outputs an aggregated cycle complete signal in response to the cycle complete signals from the first and second dynamic reconfigurable clock dividers. The interface provides reconfiguration commands to the first dynamic reconfigurable clock divider changing frequency and/or phase of the first clock output signal. The first counter maintains the frequency and phase until receiving the aggregated cycle complete signal from the AND logic gate, and then implementing the changed frequency and/or phase.

A system is provided for dynamically reconfiguring clock output signals, without clock loss and glitches. The system includes an oscillator generating a clock input signal, first and second dynamic reconfigurable clock dividers, an AND logic gate and an interface. The first and second dynamic reconfigurable clock dividers include counters that output first and second clock output signals having multiple periodic cycles, respectively, and cycle complete signals in response to completion of each periodic cycle. The AND logic gate outputs an aggregated cycle complete signal in response to the cycle complete signals from the first and second dynamic reconfigurable clock dividers. The interface provides reconfiguration commands to the first dynamic reconfigurable clock divider changing frequency and/or phase of the first clock output signal. The first counter maintains the frequency and phase until receiving the aggregated cycle complete signal from the AND logic gate, and then implementing the changed frequency and/or phase.

A power supply device for supplying power to a server and a power supply management system are provided. The device includes: a power supply control chip, a first connector, a voltage comparator, a counter and a resistance regulation circuit. The resistance regulation circuit includes a pull-up resistance circuit and a pull-down resistance circuit including multiple resistor branches and switches. An input terminal of the voltage comparator is connected to an address input terminal, the other input terminal of the voltage comparator is connected to a connection point of the resistance regulation circuit. An input terminal of the counter is connected to an output terminal of the voltage comparator, each output terminal of the counter is connected to one switch and controls a state of the switch. Each output terminal of the counter is connected to one address pin of the power supply control chip.

A power supply device for supplying power to a server and a power supply management system are provided. The device includes: a power supply control chip, a first connector, a voltage comparator, a counter and a resistance regulation circuit. The resistance regulation circuit includes a pull-up resistance circuit and a pull-down resistance circuit including multiple resistor branches and switches. An input terminal of the voltage comparator is connected to an address input terminal, the other input terminal of the voltage comparator is connected to a connection point of the resistance regulation circuit. An input terminal of the counter is connected to an output terminal of the voltage comparator, each output terminal of the counter is connected to one switch and controls a state of the switch. Each output terminal of the counter is connected to one address pin of the power supply control chip.

A processing circuit including a first oscillation circuit, a second oscillation circuit, a counting circuit, and a control circuit is provided. The first oscillation circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillation circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage. The counting circuit adjusts a first counter value according to the first clock signal and adjusts a second counter value according to the second clock signal. The control circuit receives the output voltage and determines whether the input voltage is experiencing an attack according to the first counter value and the second counter value. The first oscillation circuit operates in an un-protected power domain. The second oscillation circuit, the counting circuit, and the control circuit operate in a protected power domain.

A processing circuit including a first oscillation circuit, a second oscillation circuit, a counting circuit, and a control circuit is provided. The first oscillation circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillation circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage. The counting circuit adjusts a first counter value according to the first clock signal and adjusts a second counter value according to the second clock signal. The control circuit receives the output voltage and determines whether the input voltage is experiencing an attack according to the first counter value and the second counter value. The first oscillation circuit operates in an un-protected power domain. The second oscillation circuit, the counting circuit, and the control circuit operate in a protected power domain.