A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.

A semiconductor apparatus includes a first clock path which generates a first output clock signal by delaying a first phase clock signal, and a second clock path which generates a second output clock signal by delaying a second phase clock signal based on a delay compensation signal. The oscillating path generation circuit forms oscillating paths with the first clock path and the second clock path. The delay information generation circuit generates a delay compensation signal based on oscillating signals generated by forming the oscillating paths.

Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in power converters, the apparatus comprising: a first single shot circuit to, during runtime of a power converter, generate a clock signal based on an adaptive delay, the adaptive delay based on a count value of a counter; a pulse comparator coupled to an adaptation pulse generator, the pulse comparator to, during runtime of the power converter: compare a first duration of the adaptation pulse to a second duration of a reference pulse; and adjust the count value of the counter; and a ready detector coupled to the pulse comparator, the ready detector to, in response to a trigger event, transmit, during runtime of the power converter, the count value to a second single shot circuit.

Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in power converters, the apparatus comprising: a first single shot circuit to, during runtime of a power converter, generate a clock signal based on an adaptive delay, the adaptive delay based on a count value of a counter; a pulse comparator coupled to an adaptation pulse generator, the pulse comparator to, during runtime of the power converter: compare a first duration of the adaptation pulse to a second duration of a reference pulse; and adjust the count value of the counter; and a ready detector coupled to the pulse comparator, the ready detector to, in response to a trigger event, transmit, during runtime of the power converter, the count value to a second single shot circuit.

Disclosed herein are related to a system and a method for synchronizing signal processing on audio channels. In one aspect, a system includes processors, each including an audio data input configured to receive audio data from multiple audio sources. In one aspect, each processor includes audio channels coupled to the audio data input, where each audio channel includes a corresponding processing chain configured to convert a sample rate of audio data from a corresponding audio source. Each processor may include a synchronization pulse generator configured to generate a corresponding synchronization pulse for each processing chain in response to a trigger pulse. The synchronization pulse generator may include a counter configured to generate an output having a phase based on a programmable initial condition of the counter, where the synchronization pulse for each processing chain is based on the counter output and a phase register value of the corresponding processing chain.

Disclosed herein are related to a system and a method for synchronizing signal processing on audio channels. In one aspect, a system includes processors, each including an audio data input configured to receive audio data from multiple audio sources. In one aspect, each processor includes audio channels coupled to the audio data input, where each audio channel includes a corresponding processing chain configured to convert a sample rate of audio data from a corresponding audio source. Each processor may include a synchronization pulse generator configured to generate a corresponding synchronization pulse for each processing chain in response to a trigger pulse. The synchronization pulse generator may include a counter configured to generate an output having a phase based on a programmable initial condition of the counter, where the synchronization pulse for each processing chain is based on the counter output and a phase register value of the corresponding processing chain.

The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). An electronic device including a first radio frequency (RF) chip and a second RF chip is provided. The electronic device includes a modem configured to transmit a first clock signal to the second RF chip, the first RF chip connected to the modem and configured to receive a second clock signal from the modem, and the second RF chip electrically connected to the first RF chip through a transmission line and configured to receive the second clock signal from the first RF chip and to measure a phase of the transmission line based on the first clock signal and the second clock signal. The first clock signal and the second clock signal have different frequencies.

A photoelectric conversion apparatus includes a pulse shaping circuit that shapes an output from a diode of avalanche amplification type into a pulse, and a pulse conversion circuit that converts a pulse signal output from the pulse shaping circuit. The pulse conversion circuit converts a pulse signal having a first amplitude and output from the pulse shaping circuit into a pulse signal having a second amplitude smaller than the first amplitude.

A photoelectric conversion apparatus includes a pulse shaping circuit that shapes an output from a diode of avalanche amplification type into a pulse, and a pulse conversion circuit that converts a pulse signal output from the pulse shaping circuit. The pulse conversion circuit converts a pulse signal having a first amplitude and output from the pulse shaping circuit into a pulse signal having a second amplitude smaller than the first amplitude.

In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.