A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature signal of the first output signal.

A pulse output device which corrects a pulse signal advanced or delayed from a timing prescribed by a control device and a control system including the pulse output device are provided. A PLC system including a driving device, a CPU unit, and a pulse output unit is provided. The pulse output unit includes a clock generation unit that generates a clock signal, a pulse output unit that generates a pulse signal by dividing a frequency of a clock signal and outputs the pulse signal having the number of pulses and a pulse speed commanded by the CPU unit at a prescribed timing, a pulse counter that counts the number of pulses of the output pulse signal, and a processing unit that corrects the pulse speed of the pulse signal generated by the pulse output unit based on an error in the numbers of pulses.

A pulse output device which corrects a pulse signal advanced or delayed from a timing prescribed by a control device and a control system including the pulse output device are provided. A PLC system including a driving device, a CPU unit, and a pulse output unit is provided. The pulse output unit includes a clock generation unit that generates a clock signal, a pulse output unit that generates a pulse signal by dividing a frequency of a clock signal and outputs the pulse signal having the number of pulses and a pulse speed commanded by the CPU unit at a prescribed timing, a pulse counter that counts the number of pulses of the output pulse signal, and a processing unit that corrects the pulse speed of the pulse signal generated by the pulse output unit based on an error in the numbers of pulses.

A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor device 1 includes a clock oscillator 2, a counter 3 configured to count the number of clocks, a periodic register 4 in which a value corresponding to a period for synchronization is set, a comparison circuit 5 configured to compare the count value in the counter 3 with the set value in the periodic register 4, a match flag register 6 in which a predetermined value is set when the count value coincides with the set value, a match output terminal 7 configured to output the value in the match flag register 6 from the own semiconductor device, a match input terminal 8 to which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counter 3 and the match flag register 6 when both the value in the match flag register 6 of the own semiconductor device and the value input to the match input terminal 8 become a predetermined value.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.