A battery monitoring device and a battery monitoring system for suppressing a variation of a pulse width in a communication signal transmitted and received between battery monitoring devices are provided. The battery monitoring device comprises: a receiving unit, which receives a communication signal input from the outside; a signal regenerating unit, which regenerates the communication signal so that a width of a pulse that is included in the communication signal received by the receiving unit becomes a prescribed magnitude; a transmitting unit, which transmits the communication signal regenerated by the signal regenerating unit to the outside; and a processing unit, which carries out a process of measuring a cell voltage of battery cells according to the communication signal received by the receiving unit.

A battery monitoring device and a battery monitoring system for suppressing a variation of a pulse width in a communication signal transmitted and received between battery monitoring devices are provided. The battery monitoring device comprises: a receiving unit, which receives a communication signal input from the outside; a signal regenerating unit, which regenerates the communication signal so that a width of a pulse that is included in the communication signal received by the receiving unit becomes a prescribed magnitude; a transmitting unit, which transmits the communication signal regenerated by the signal regenerating unit to the outside; and a processing unit, which carries out a process of measuring a cell voltage of battery cells according to the communication signal received by the receiving unit.

A method for manufacturing a semiconductor device includes forming a circuit including a plurality of flip-flops, a plurality of first switches, a second switch and a signal line on a wafer, the flip-flops being connected in series through the first switches, respectively, and the signal line being connected to the second switch, and being configured to supply a signal in parallel to the flip-flops; testing the flip-flops by turning off the first switches, turning on the second switch, and supplying a test signal in parallel through the signal line to the flip-flops;

and cutting at least one interconnect of a switch portion in the circuit, the switch portion including the first switches and the second switch, so that the first switch is turned on and the second switch is turned off.

A method for manufacturing a semiconductor device includes forming a circuit including a plurality of flip-flops, a plurality of first switches, a second switch and a signal line on a wafer, the flip-flops being connected in series through the first switches, respectively, and the signal line being connected to the second switch, and being configured to supply a signal in parallel to the flip-flops; testing the flip-flops by turning off the first switches, turning on the second switch, and supplying a test signal in parallel through the signal line to the flip-flops;

and cutting at least one interconnect of a switch portion in the circuit, the switch portion including the first switches and the second switch, so that the first switch is turned on and the second switch is turned off.

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

Disclosed herein is a control system for a laser scanning projector. The control system includes a mirror controller generating a mirror synchronization signal for an oscillating mirror apparatus based upon a mirror clock signal. The control system also includes laser modulation circuitry for generating a laser synchronization signal as a function of a laser clock signal, and generating control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry is for generating the laser clock signal and sending the laser clock signal to the laser modulation circuitry, receiving the mirror synchronization signal from the mirror controller, receiving the laser synchronization signal from the laser modulation circuitry, and modifying frequency and phase of the laser clock signal for the laser as a function of the mirror synchronization signal and the laser synchronization signal.

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.