A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.

A Functional Safety Counter Module is provided and it comprises input circuitry, test circuitry, a first microcontroller including a first hardware counter, a second hardware counter, a first storage device that stores a first firmware algorithm code to execute a counter pattern test in order to detect a short open input signal and/or a failure in counting capability of the first microcontroller and a second microcontroller including a third hardware counter, a fourth hardware counter, a second storage device that stores a second firmware algorithm code. The first and second firmware algorithm codes are configured to resynchronize and restore respectively a first counter or a second counter after the counter pattern test and are configured to detect an offset and adjust during a resynchronization process to account for the offset such that to successfully resynchronize two separate resynchronization algorithm codes are used depending on an input frequency of counter signals input to four hardware counters.

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

A crystal oscillator is started in a high power mode for a certain period of time to ensure starting oscillation with average grade crystals, then once the certain time period is over the oscillator switches into a low power mode and sustains oscillation with energy pulses triggered by and synchronized with the oscillator output frequency. These energy pulses may be generated on the positive, negative or both positive and negative edges of the clock output waveform.

A pulse output device which corrects a pulse signal advanced or delayed from a timing prescribed by a control device and a control system including the pulse output device are provided. A PLC system including a driving device, a CPU unit, and a pulse output unit is provided. The pulse output unit includes a clock generation unit that generates a clock signal, a pulse output unit that generates a pulse signal by dividing a frequency of a clock signal and outputs the pulse signal having the number of pulses and a pulse speed commanded by the CPU unit at a prescribed timing, a pulse counter that counts the number of pulses of the output pulse signal, and a processing unit that corrects the pulse speed of the pulse signal generated by the pulse output unit based on an error in the numbers of pulses.

A pulse output device which corrects a pulse signal advanced or delayed from a timing prescribed by a control device and a control system including the pulse output device are provided. A PLC system including a driving device, a CPU unit, and a pulse output unit is provided. The pulse output unit includes a clock generation unit that generates a clock signal, a pulse output unit that generates a pulse signal by dividing a frequency of a clock signal and outputs the pulse signal having the number of pulses and a pulse speed commanded by the CPU unit at a prescribed timing, a pulse counter that counts the number of pulses of the output pulse signal, and a processing unit that corrects the pulse speed of the pulse signal generated by the pulse output unit based on an error in the numbers of pulses.

A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.

A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.

The present application relates to a system hosting a monotonic counter and a method of operating the system. The system comprises a non-volatile memory (110) for holding a save counter value and a volatile memory (120) for maintaining a current counter value. The system (100) is configured during a startup phase to retrieve the saved counter value of the monotonic counter from the non-volatile memory (110); to detect whether a previous shutdown of the system (100) was an uncontrolled shutdown; and to adjust the retrieved counter value in accordance with a step size (130) provided at the system (100) in case an previous uncontrolled shutdown is detected.