An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window from the clock signal input. The first sampled window includes an accumulation of the N time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.

Various embodiments provide for verifying operation of a circuit design with respect to a data communication specification, such as a DisplayPort specification, with Low-Frequency Periodic Signaling (LFPS) pulse detection using unit interval adjustment based on an average pulse width of detected LFPS pulses.

Various embodiments provide for verifying operation of a circuit design with respect to a data communication specification, such as a DisplayPort specification, with Low-Frequency Periodic Signaling (LFPS) pulse detection using unit interval adjustment based on an average pulse width of detected LFPS pulses.

A battery monitoring system that monitors states of a plurality of batteries. The battery monitoring system includes a battery monitoring ECU and a plurality of battery monitoring devices. The battery monitoring ECU and the plurality of battery monitoring devices are connected to each other in any connection form of ring connection, daisy chain connection, or multi-drop connection.

An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window based upon a first time measurement and a first previous time measurement received m time measurements earlier than the first time measurement. The sampling circuit is to generate a second sampled window based upon a second time measurement and a second previous time measurement received m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.

An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window based upon a first time measurement and a first previous time measurement received m time measurements earlier than the first time measurement. The sampling circuit is to generate a second sampled window based upon a second time measurement and a second previous time measurement received m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.

A clock divider and a clock division method using the same for maintaining a constant output clock duty regardless of a divide value change timing are provided. The clock divider includes a counter configured to count an input clock to generate a counter output based on a count of a first counter expiration value corresponding to a divide value of the clock, an output clock generator configured to generate an output clock divided from the input clock according to the counter output of the counter, and a state machine configured to update the counter to a second counter expiration value corresponding to a changed divide value depending on whether the first counter expiration value has expired based on the divide value being changed.

A clock divider and a clock division method using the same for maintaining a constant output clock duty regardless of a divide value change timing are provided. The clock divider includes a counter configured to count an input clock to generate a counter output based on a count of a first counter expiration value corresponding to a divide value of the clock, an output clock generator configured to generate an output clock divided from the input clock according to the counter output of the counter, and a state machine configured to update the counter to a second counter expiration value corresponding to a changed divide value depending on whether the first counter expiration value has expired based on the divide value being changed.

Aspects of the subject disclosure may include, for example, a track-and-hold sampling circuit, having: a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals; and a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal. Other embodiments are disclosed.

Aspects of the subject disclosure may include, for example, a track-and-hold sampling circuit, having: a duty-cycle limiter that generates a clock signal having a duty cycle that is less than 100% from three out of four clock signals; and a sampling circuit comprising complementary positive and negative input gates that track and sample data input signals, wherein the sampling circuit generates sampled data signals, wherein the complementary positive and negative input gates are coupled to the clock signal. Other embodiments are disclosed.