A capacitive digital isolator circuit includes: a signal emitting module; a signal receiving module; and a capacitive isolation module. The signal emitting module includes an edge Pulse-Coding modulator circuit, which modulates an input signal to generate a pair of differential modulated signals based on the input signal and transmits the pair of differential modulated signals to the signal receiving module. Each of the pair of differential modulated signals has twelve high-frequency pulses when the input signal has a rising edge and has six high-frequency pulses when the input signal has a falling edge. The signal receiving module includes an ultra-low power consumption high-speed comparator, a timer and a pulse counter. An output signal of the pulse counter has a rising edge when the pulse number of the comparator output signal is larger than nine and a falling edge when the pulse number is equal to or smaller than nine.

The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.

The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.

An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

A battery monitoring device and a battery monitoring system for suppressing a variation of a pulse width in a communication signal transmitted and received between battery monitoring devices are provided. The battery monitoring device comprises: a receiving unit, which receives a communication signal input from the outside; a signal regenerating unit, which regenerates the communication signal so that a width of a pulse that is included in the communication signal received by the receiving unit becomes a prescribed magnitude; a transmitting unit, which transmits the communication signal regenerated by the signal regenerating unit to the outside; and a processing unit, which carries out a process of measuring a cell voltage of battery cells according to the communication signal received by the receiving unit.

A battery monitoring device and a battery monitoring system for suppressing a variation of a pulse width in a communication signal transmitted and received between battery monitoring devices are provided. The battery monitoring device comprises: a receiving unit, which receives a communication signal input from the outside; a signal regenerating unit, which regenerates the communication signal so that a width of a pulse that is included in the communication signal received by the receiving unit becomes a prescribed magnitude; a transmitting unit, which transmits the communication signal regenerated by the signal regenerating unit to the outside; and a processing unit, which carries out a process of measuring a cell voltage of battery cells according to the communication signal received by the receiving unit.

A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.