A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.

Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.OSC, wherein f.sub.OSC is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

A counting control circuit includes a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit is connected to a clock terminal of the counting statistic circuit. The logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal. The counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal which indicates a generation of a command signal for performing a first operation, here, the first identification signal is in a valid state when a counting value meets a preset condition.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising: i) a multiplier device (110), configured to receive a single-ended incoming signal (105), and multiply the incoming signal (105) to provide a multiplied signal (115); and ii) a divider device (120), configured to receive the multiplied signal (115), and divide the multiplied signal (115) to provide a differential signal (125a, 125b). Further, a corresponding signal conversion method is described.

This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.