A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number.

A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number.

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system

Temporal history of voltage supply level enveloping high-speed transient events is provided by circuitry on the same chip or in the same multi-chip module as the processor cores. In some embodiments supply voltage to the processor cores is compared to predetermined or programmable thresholds, and the result of the comparisons are stored for use by a host processor.

Temporal history of voltage supply level enveloping high-speed transient events is provided by circuitry on the same chip or in the same multi-chip module as the processor cores. In some embodiments supply voltage to the processor cores is compared to predetermined or programmable thresholds, and the result of the comparisons are stored for use by a host processor.