A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor 103 generates a mechanical force that drives a component. A ripple count circuit 104 is configured to filter the drive current based on a rotational speed (ω) of the rotor 103 to generate a filtered drive current signal, and to generate a varying threshold based on the filtered drive current signal. Based on a comparison between the filtered drive current signal and the varying threshold, the ripple count circuit 104 generates a pulsed output signal indicative of the rotational speed (ω) of the rotor and a rotational position (θ) of the rotor.

An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

In a PLL circuit, first an ILFD is connected to an output voltage Vtune from an LPF, thereby causing the ILFD to operate as an oscillator. The ILFD, a DIV, PFD, CP, and LPF form a PLL and thereby locking operations are initiated. When a predetermined time elapses, an output frequency from the ILFD converges into a certain value and the PLL is subjected to a locked state. After the locked state is reached, a sample hold circuit SH holds the output voltage Vtune from the loop filter as of that time and frequency adjustment of the ILFD is completed. Similar frequency adjustment is sequentially performed on other ILFDs.

In a PLL circuit, first an ILFD is connected to an output voltage Vtune from an LPF, thereby causing the ILFD to operate as an oscillator. The ILFD, a DIV, PFD, CP, and LPF form a PLL and thereby locking operations are initiated. When a predetermined time elapses, an output frequency from the ILFD converges into a certain value and the PLL is subjected to a locked state. After the locked state is reached, a sample hold circuit SH holds the output voltage Vtune from the loop filter as of that time and frequency adjustment of the ILFD is completed. Similar frequency adjustment is sequentially performed on other ILFDs.

A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhanced operation speed and reduced power consumption.