A motor control system includes a DC motor and a ripple count circuit. The DC motor includes a rotor that rotates in response to a drive current. The rotation of the rotor generates a mechanical force that drives a component. The ripple count circuit includes an active filter circuit and a parasitic pulse cancellation circuit. The active filter circuit is configured to filter the drive current and to generate a pulsed signal. The parasitic pulse cancelation circuit is in signal communication with the ripple count circuit to receive the pulsed signal and generates a ripple count signal that excludes parasitic pulses included in the pulsed signal having a parasitic voltage level that exceeds a voltage level of a voltage threshold. The parasitic pulse cancelation circuit actively adjusts the voltage level of the voltage threshold based at least in part on a rotational direction of the rotor.

A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

An apparatus is described. The apparatus includes a counter circuit having ordered state element circuits where a respective clock input of a state element circuit is fed by a data output of a preceding lower ordered bit state element. The counter circuit also being programmable to enable different amounts to be counted by the counter circuit, wherein respective reload values for the amounts are received at the state elements as a respective asynchronous set or reset.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.

Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.