A bidirectional switch fault protection circuit includes a bidirectional switch circuit, a desaturation detection circuit, and a gate driver. The bidirectional switch circuit generates first and second switch voltages based on a direction of electric current. The desaturation detection circuit outputs the first switch voltage in response to the electric current flowing in a first direction and outputs the second switch voltage in response to the electric current flowing in a second direction opposite the first direction. The gate driver receives the first switch voltage in response to the electric current flowing in the first direction and the second switch voltage in response to the electric current flowing in the second direction. The gate driver detects a first short circuit condition based on the first switch voltage and a second short circuit condition based on the second switch voltage.

An electronic protection switch includes first and second network terminals and two semiconductor switches of same kind. Each semiconductor switch is formed by an IGBT semiconductor switch and includes a switching element and a diode which is arranged antiparallel to the switching element. A first of the two semiconductor switches is arranged without a semiconductor series connection between a positive potential terminal of the first network terminal and a positive potential terminal of the second network terminal. A second of the two semiconductor switches is arranged without a semiconductor series connection between a negative potential terminal of the first network terminal and a negative potential terminal of the second network terminal. The switching element of each semiconductor switch is arranged so as to be able to conduct and switch off a current from the first network terminal to the second network terminal.

According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.

A load control device for controlling power delivered from an AC power source to an electrical load may have a closed-loop gate drive circuit for controlling a semiconductor switch of a controllably conductive device. The controllably conductive device may be coupled in series between the source and the load. The gate drive circuit may generate a target signal in response to a control circuit. The gate drive circuit may shape the target signal over a period of time and may increase the target signal to a predetermined level after the period of time. The gate drive circuit may receive a feedback signal that indicates a magnitude of a load current conducted through the semiconductor switch. The gate drive circuit may generate a gate control signal in response to the target signal and the feedback signal, and render the semiconductor switch conductive and non-conductive in response to the gate control signal.

Intelligent electrical switches are provided to implement multi-way circuits using two or more intelligent electrical switches for controlling power to a load.

Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

There may be two active snubbers for direct current (dc) solid-state circuit breakers (SSCBs): metal-oxide-varistor with resistor-capacitor-switch (MOV-RCS) and active-MOV with resistor-capacitor-diode (AMOV-RCD). In the snubber branch, either half- or full-controlled switch can be used, leading to four topologies. The improved snubbers offer several improvements: 1) MOV is disconnected from the power line during SSCB OFF-state, which enhances reliability as neither voltage nor power appears on MOV; 2) voltage utilization rate ηv of the main switch is remarkably increased, which improves efficiency and power density, and reduces design cost shows experiments of five prototypes are conducted including four proposed snubbers and a comparison with conventional MOV-RCD snubber.

A bidirectional GaN FET with a single gate formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs with a common source. The single-gate bidirectional GaN FET occupies most of the integrated circuit die, such that the integrated device has a low channel resistance, while also capturing the advantages of a back-to-back bidirectional GaN FET device.

A power supply device is provided. The power supply device includes a first switch element for selectively providing an alternating current (AC) power source to an actuation device, a second switch element for selectively providing the AC power source to the first switch element, a detection circuit for confirming whether or not the first switch element is in a full turn-on state, by comparing an input power source and an output power source of the first switch element, a sensor for sensing the size of the AC power source, and a controller for selectively controlling the operation of the second switch element on the basis of the sensed size of the AC power source and the confirmed full turn-on state.

A doorbell chime bypass circuit includes a first node, a second node, and a bi-directional FET switch in series with the first node and the second current node. The bi-directional FET switch includes a first FET and a second FET in series, and is configured to cease conducting current between the first and second nodes when gate voltages of the first and second FETs are below a cut-off threshold. The bypass circuit further includes a sensing circuit configured to determine a level of current flowing through the bi-directional FET switch, and a switch controller configured to set the gate voltages of the first and second FETs to a level below the cut-off threshold when the sensing circuit senses that the level of current meets a doorbell press current threshold, causing the bi-directional FET switch to cease conducting current between the first and second nodes.