A wireless communication device can include switch circuitry. The switch circuitry can include stacks having a common gate node and a common body node, wherein a stack includes a metal-oxide-semiconductor field-effect transistor (MOSFET) having a body resistive element coupled to a body terminal of the MOSFET and the common body node a gate resistive element coupled to a gate terminal of the MOSFET and the common gate node. The switch circuitry can further include a self-biased MOSFET coupled to the common gate node and the common body node, a gate of the self-biased MOSFET configured to receive direct current (DC) bias with a low pass filter.

A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.

Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

According to various aspects, a latch-type charge pump may include: an input node and an output node; a first charge storage and a second charge storage coupled in parallel to each other, a first switch coupled to the input node and a second switch coupled to the output node, wherein the first charge storage couples the first switch with the second switch; and a control circuit configured to control the first switch based on a state of the second charge storage, and to control the second switch based on a state of the first charge storage.