An apparatus includes a first gate drive transistor and a second gate drive transistor connected in series, a common node of the first gate drive transistor and the second gate drive transistor connected to a gate of a power switch, the second gate drive transistor configured as a bulk switch having a bulk terminal connected to a bulk terminal of the power switch, a first auxiliary transistor connected between the bulk terminal and a source of the power switch, a second auxiliary transistor coupled between the gate of the power switch and a system ground, and a third auxiliary transistor coupled between a logic control ground and the system ground, wherein the second auxiliary transistor and the third auxiliary transistor are configured to pull the gate of the power switch and the logic control ground down to the system ground in response to a turn off of the apparatus.

An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT<VSH≤(2×VGT), in a case where the enable signal is 0, the second gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of a PMOS when the control signal is 0, and the first gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of an NMOS when the control signal is 1.

A switch device for switching an analog electrical input signal includes: a switching transistor being a flipped-well-silicon-on-insulator-NMOS transistor; and a bootstrapping arrangement including a voltage providing arrangement for providing a floating voltage during the on-state, wherein the floating voltage is provided at a positive terminal and at a negative terminal of the voltage providing arrangement; wherein the bootstrapping arrangement is configured in such way that during the on-state the positive terminal is electrically connected to the front gate contact of the switching transistor and to the back gate contact of the switching transistor, and the negative terminal is electrically connected to the source contact of the switching transistor; wherein the bootstrapping arrangement is configured in such way that during the off-state the positive terminal and the negative terminal are not electrically connected to the switching transistor.

Stabiliser circuits and methods are disclosed, for stabilizing a voltage at a gate driver terminal of a gate-driver for a driven transistor to a one of a high voltage and a low voltage, the stabilizer circuit comprising: a first transistor and a second transistor having respective first and second main terminals and connected in series between the gate voltage terminal and a first reference voltage terminal; and a low-pass filter connected between a control terminal of the first transistor and the gate driver terminal; wherein the first transistor is configured to have a threshold voltage which is less that a threshold voltage of the driven transistor; and the second transistor has a control terminal which is configured to be connected to a voltage which is an oppositive of the voltage at the gate driver terminal.

A charge pump cell for a charge pump is disclosed that may exhibit improved latch-up immunity. A circuit may be arranged at the charge pump cell to apply a voltage to a bulk contact of a charge transfer transistor of such a charge pump cell at least partially responsive to a relationship between a voltage at a first terminal of the charge transfer transistor and a voltage at a second terminal of the charge transfer transistor. A charge pump including one or more such charge pump cells may include a control loop that is configured to control a pumping signal at least partially responsive to a state of an output voltage of the charge pump.

A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.

RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.

A semiconductor device includes a semiconductor body having an active region and a substrate region that is disposed beneath the active region, and a bidirectional switch formed in the semiconductor body. The bidirectional switch includes first and second gate structures that are each configured to control a conductive state of an electrically conductive channel that is disposed in the active region, and first and second input-output terminals that are each in ohmic contact with the electrically conductive channel. A passive substrate voltage discharge circuit in parallel with the bidirectional switch is configured to discharge a voltage of the substrate region in both directions of the bidirectional switch. The passive substrate voltage discharge circuit includes first and second normally-on switches connected in anti-series between the first and second input-output terminals in a common source configuration with the substrate region as a midpoint.

A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are formed on the substrate. The first doped region is formed in the first well. The second doped region is formed in the second well. The gate electrode is disposed over the substrate. The gate electrode, the first doped region, and the second doped region constitute a transistor. The insulating layer is disposed on the substrate and overlaps the gate electrode. The field plate overlaps the insulating layer and the gate electrode. The tunable circuit provides either a first short-circuit path between the field plate and the gate electrode, or a second short-circuit path between the field plate and the first doped region.