A switching device includes a first leg having a plurality of transistors connected in series. The switching device also includes a second leg having a transistor, where the second leg is connected in parallel to plurality of transistors of the first leg. The switching device further includes a third leg having a diode, and the third leg has lower reverse recovery losses relative to the first leg and/or the second leg.

Disclosed herein is a bridge rectifier and associated control circuitry collectively forming a “regtifier”, capable of both rectifying an input time varying voltage as well as regulating the rectified output voltage produced. To accomplish this, the gate voltages of transistors of the bridge rectifier that are on during a given phase may be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors prior to the end of the phase). Alternatively or additionally, the transistors of the bridge rectifier that would otherwise be off during a given phase may be turned on to help dissipate excess power and thereby regulate the output voltage. A traditional voltage regulator, such as a low-dropout amplifier, is not used in this design.

According to one embodiment, a current detecting circuit includes: a normally-ON type first switching element that includes a drain, a source, and a gate; a normally-OFF type second switching element including a drain that is connected to the source of the first switching element, a source that is connected to the gate of the first switching element, and a gate; and a differential amplification circuit that outputs a voltage according to a voltage between the drain and the source of the second switching element.

Proposed is a drive circuit including: a driving NMOS transistor having a source set to a reference potential and a driving PMOS transistor having a source set to a first potential, the driving NMOS transistor and the driving PMOS transistor having a mutually common drain connected to a load; a first bipolar transistor configured to control on/off of the driving PMOS transistor; a first switching element that causes conduction or non-conduction between a gate and the source of the driving NMOS transistor; and a second switching element that causes conduction or non-conduction between a gate and the source of the driving PMOS transistor.

A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

Embodiments of the present disclosure are related to a gate circuit and a display device. By disposing a bootstrap capacitor between a Q1 node which is different from a Q node and an input terminal of a gate clock signal used for outputting a scan signal, a voltage level of the Q1 node can be maintained stably at an output timing of the scan signal. Thus, a driving state of a switching transistor which is controlled by the Q1 node and controls a QB node can be controlled stably, and thus a defect of refreshing of the QB node can be prevented and the scan signal can be output stably, thereby a reliability of the gate circuit can be improved.

A DC-DC switching converter includes power switches selectively coupling an output terminal with a first voltage or with a second voltage. A driver stage is coupled with the power switches for driving the power switches. A driver control stage is coupled with the driver stage for controlling the operation of the driver stage. An output current sensing circuit is coupled with the output terminal and with the driver control stage, and is configured to sense a sign of an output current delivered by the DC-DC switching converter at the output terminal and to generate control signals for the driver control stage. The driver control stage controls the operation of the driver stage according to states of the control signals received from the output current sensing circuit, for selectively delaying the activation of the power switches depending on the sensed sign of the output current.

An over-current protection circuit for limiting a power current flowing through a switch device, which generates the power current according to a control signal of a control node, is provided. The over current control circuit includes a voltage control circuit, a current sense unit, a conversion circuit, and a control switch. The voltage control circuit provides the control signal to a gate terminal of the switch device according to a limit signal. The current sense unit senses the power current flowing through the switch device to generate a sense voltage. The conversion circuit converts the sense voltage into a conversion voltage. The control switch generates the limit signal according to the conversion voltage.

Gate driver bootstrap circuits and related methods are disclosed. An example gate driver stage includes a first terminal and a second terminal, the first terminal to be coupled to a capacitor, the capacitor and the second terminal to be coupled to a gate terminal of a power transistor, a gate driver coupled to the first terminal and the second terminal, and a bootstrap circuit coupled to the first terminal, the second terminal, and the gate driver, the bootstrap circuit including a control stage circuit having an output and a first transistor having a first gate terminal and a first current terminal, the first gate terminal coupled to the output, the first current terminal coupled to the first terminal.

A circuit can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using one or more JJ-based current sources.