Apparatus and methods for multi-gate radio frequency (RF) switches are disclosed herein. The RF switches use various layout design techniques to improve figure of merit (FOM). Examples of such techniques include using only two field-effect transistors (FETs) in series to maintain shorter fingers for lower metal resistance, placing a body contact on only one side of the RF switch layout, implementing metallization with reduced coupling from input to output, and/or providing air gaps to improve high frequency performance.

A drive apparatus that drives a control terminal of a main switching element establishing/cutting off an electrical connection between a first main terminal and a second main terminal is provided, including first to fourth switching elements establishing/cutting off electrical connections between a positive terminal of a power source and the control terminal, the positive terminal and the second main terminal, the control terminal and a negative terminal of the power source, and the second main terminal and the negative terminal, respectively, and a resistance of at least one among a path between the control terminal and the second main terminal via the first to second switching elements, a path via the first and fourth switching elements, a path via the second to third switching elements, and a path via the third to fourth switching element is different from a resistance of at least one of the others.

The present disclosure relates to a circuit arrangement which comprises one high-efficiency fully soft-switching single-stage 3-level power amplifier with dual auxiliary networks. The primary-side passive auxiliary network is formed by one inductor and two capacitors to extend soft switching ranges and avoid switching loss. The secondary-side active auxiliary network is constituted of four switches, three capacitors and two inductors which not only removes or maximally reduces otherwise occurring disruptive spikes but also assists zero voltage switching (ZVS) for switches of active auxiliary network. A predictive gate drive method for driving power switches is presented to guarantee ZVS turn-on. The proposed circuit achieves high level of integration without bulky dc link capacitor, and high-efficiency by single-stage conversion and ZVS for all the switches under different operating conditions.

To suppress a leakage current flowing through a parasitic capacitor of an insulated transformer of a high-side insulated power. The present invention suppresses a common mode current using a common mode reactor by focusing on the fact that a leakage current flowing through a parasitic capacitor of an insulated transformer of a high-side insulated power source resulting from a high-frequency signal generated due to an on/off operation of a high-side switching element is the common mode current. The common mode reactor reduces the common mode current and bears the high-frequency signal to prevent the high-frequency signal from being applied to the insulated transformer of the high-side insulated power source, suppress the leakage current flowing through the parasitic capacitor of the insulated transformer, and reduce an erroneous operation of the high-side switching element generated due to the leakage current flowing through the parasitic capacitor of the insulated transformer.

Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

A load driving device includes an H bridge circuit that includes a first upstream switching element, a first downstream switching element, a second upstream switching element, a second downstream switching element, a first output terminal between the first upstream switching element and the second downstream switching element, and a second output terminal between the second upstream switching element and the first downstream switching element. A first load is connected between the first output terminal and the second output terminal, and a second load is connected between a ground potential point and one of the first output terminal and the second output terminal.

A semiconductor device comprises a first transistor with a silicon carbide layer between the source and the drain electrodes and between the gate and drain electrodes. A diode is formed in the silicon carbide layer. A forward voltage of the diode varies with the voltage applied to the gate electrode of the first transistor. A second transistor is connected to the first transistor. A gate controller applies voltages to gates of the first and second transistor such that the first and second transistors are set to an off-state a first time. The first gate voltage is then increased to an intermediate voltage that is less than a threshold voltage of the first transistor. The intermediate voltage is sufficient to alter the forward voltage of the diode and permit a forward current to flow in the diode. The first gate voltage is then increased to an on-state voltage.

A driving apparatus includes a current output unit, a reference voltage output unit, a comparator, and a drive control unit. The current output unit is switchable to either a first ON resistance or a second ON resistance that is N times (N>1) the first ON resistance. The reference voltage output unit outputs a fist reference voltage during a large current time period, and outputs a second reference voltage that is M times (M>1) the first reference voltage during a small current time period. The drive control unit performs control to perform switching to the first ON resistance during the large current time period, and to perform switching to the second ON resistance during the small current time period.

Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

A regenerative current detection circuit includes a first power MOS transistor that is configured as a current mirror to a second power MOS transistor connected to drive a motor winding, a first feedback amplifier that compares a first regenerative current that flows in the first power MOS transistor with a second regenerative current that flows in the second power MOS transistor and outputs a comparison result, the first regenerative current being obtained by multiplying the second regenerative current by a current mirror ratio, and a current detection circuit that outputs a detection current based on the comparison result.