A high-voltage semiconductor switch is provided. The high-voltage semiconductor switch comprises one or more switch subcircuits, wherein each switch subcircuit may comprise one or more FET circuits and voltage-shifting transistor. The high-voltage semiconductor switch may be configured based on operational and environmental requirements, such as those of a quantum computing system, wherein the high-voltage switch may be located in a cryostat or vacuum chamber.

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

The present disclosure relates to a solid insulated switch using a semiconductor comprising a main circuit unit connected between systems on both sides thereof, and which has a first semiconductor and a second semiconductor arranged in a series; a snubber circuit having a capacitor and a resistor arranged in a series, one end connected in parallel to the front end of the first semiconductor switch, and the other end connected in parallel to the rear end of the second semiconductor switch; a freewheeling circuit, having a diode and a resistor arranged in a series, one end connected to a common contact between the first semiconductor switch and the second semiconductor switch, and the other end connected to the ground; and a mechanical switch for ensuring physical insulation after fault current interruption.

An apparatus includes a first leg having a plurality of transistors connected in series between a first node and a second node. Each of the plurality of transistors includes a respective body diode. The apparatus further includes a second leg connected between the first node and the second node and in parallel to the series connection of the plurality of transistors of the first leg. The second leg includes a first transistor. The second leg has lower reverse recovery losses relative to the first leg.

According to one embodiment, a semiconductor device includes a first circuit, a first terminal, a second terminal, a conductor and a first switch element serially coupled between the first terminal and the second terminal, wherein the first circuit is configured to turn the first switch element to an OFF state when a first condition is satisfied, and the conductor is configured to physically break when a second condition is satisfied.

A power circuit with a first transistor, including a first terminal connected to a first node, a second terminal connected to an input node, and a control terminal connected to a first control node, and a second transistor, including a first terminal connected to the first node, a second terminal connected to an output node, and a control terminal connected to a second control node. A third transistor includes a first terminal connected to the first control node, a second terminal connected to a second node, and a control terminal, and a fourth transistor includes a first terminal connected to the output node, a second terminal connected to the second control node, and a control terminal connected to a third node. The power circuit also includes a current limiting circuit coupled between the second node and the third node.

An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.