A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.

A wireless communication device can include switch circuitry. The switch circuitry can include stacks having a common gate node and a common body node, wherein a stack includes a metal-oxide-semiconductor field-effect transistor (MOSFET) having a body resistive element coupled to a body terminal of the MOSFET and the common body node a gate resistive element coupled to a gate terminal of the MOSFET and the common gate node. The switch circuitry can further include a self-biased MOSFET coupled to the common gate node and the common body node, a gate of the self-biased MOSFET configured to receive direct current (DC) bias with a low pass filter.

A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

An electronic device includes an electronic component, a driving circuit and a circuit. The driving circuit is electrically connected between a node and a first voltage. The electronic component is electrically connected between the node and a second voltage. The circuit is electrically connected between the node and a third voltage. The first voltage is different from the second voltage and the third voltage.

Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

A monolithically integrated bidirectional switch includes: an output terminal; a control terminal; a compound semiconductor substrate; a common drift region in the compound semiconductor substrate and in series between the input terminal and the output terminal; a first gate; and a second gate. The first gate is electrically connected to the control terminal and the second gate is electrically connected to the input terminal, or one of the first gate and the second gate is a normally-on gate and the other one of the first gate and the second gate is a normally-off gate. In either case, the monolithically integrated bidirectional switch is configured to conduct current in a single direction from the input terminal to the output terminal through the common drift region. A corresponding power electronic system that uses the monolithically integrated bidirectional switch is also described.